Custom Layout Engineer

AdoreSys; Bayan Lepas; On-site; MYR 70,000 - 100,000; Full time

Job summary

AdoreSys is seeking a versatile Custom Layout Engineer to shape the physical implementation of diverse circuitry, including Foundation IP, Analog IP, and RF blocks. You’ll own floorplanning, layout construction, verification, and QA, ensuring on‑time delivery while optimizing Power, Performance & Area (PPA).

Candidates should have 2–7 years in custom IC layout, DRM expertise, and proficiency with Synopsys/Cadence tools. This role welcomes senior candidates as well.

Qualifications

• Bachelor’s degree in Electrical, Electronic, or Materials Science Engineering.
• 2–7 years of hands-on custom IC layout experience with finFET/GAA process nodes.
• Strong understanding of DRM, CMOS tech, and DFM issues for high‑performance layouts.
• Proficient in layout editors (Synopsys/Cadence) and physical verification tools.
• Team player with cross‑site communication and time management.

Responsibilities

• Realize physical implementation including floorplanning, layout construction.
• Perform physical verification and QA flow sign‑off for layouts.
• Provide timely project status updates and mitigate execution risks.
• Collaborate with multi‑functional teams to optimize layout for PPA.

Skills

Layout debugging

Cross‑team collaboration

Time management

Analytical thinking

Education

Bachelor’s in Electrical, Electronic, or Materials Science Eng.

Tools

Synopsys/Cadence layout editor

DRC/LVS/ERC verification tools

Job description

Level: Junior/Senior/Staff/Technical Lead

Overview:

Are you passionate about driving innovation in microchip design? Ready to take the lead in shaping the next generation of integrated circuits? We’re looking for a variety of positions for Custom Layout Engineer to join our team and make a significant impact on advanced semiconductor technology—including the chips powering tomorrow’s AI breakthroughs.

What you’ll do:

• Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP, and RF building blocks.
• Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning, layout construction, physical verification and QA flow sign-off.
• Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery for each project.
• Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area (PPA).

Who we’re looking for:

• Bachelor’s degree in Electrical, Electronic, or Material Science Engineering.
• More than 2~7 years of hands‑on experience in custom IC layout for Standard Cell, Memory Compiler or IO/ESD libraries using advanced finFET/GAA process nodes; candidates with Analog/RF experiences are welcomed to apply.
• Proficient in understanding DRM of advanced CMOS technologies and have a good grasp of deep sub‑micron and DFM issues for high‑performance layout designs.
• Analytical and skillful in debugging physical verification checks (eg. DRC/LVS/ERC, etc.).
• Proficient in Synopsys/Cadence layout editor and physical verification tools.
• Team player and effective in cross‑team communication and time management.
• Experienced candidate will be considered for senior position.

Ready to help build the chips that will power the future of AI?