Lead Mask Design Engineer - Advanced Si Layout & Packaging

UST; Seberang Perai; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST in Malaysia seeks an experienced IC layout engineer to execute high density Si layout designs for EMIB, interposer and test chips. You will create custom IC layouts to specification and run comprehensive verification including DRC/LVS and reliability checks.

The role requires 7+ years of IC layout experience, proficiency with Cadence Virtuoso, and strong problem-solving skills to troubleshoot complex layout issues and optimize flows.

Qualifications

• Bachelor's degree in Electronics Engineering or related field.
• 7+ years of experience in IC layout/design.
• Experience with advanced packaging elements and Si manufacturing nodes.
• Proficient with Cadence Virtuoso.

Responsibilities

• Execute high density Si layout designs across advanced packaging elements (EMIB, Interposer, Test Chips).
• Create custom IC layouts to specification and run full verification (DRC, LVS, reliability checks).
• Analyze input bumps/floorplans, layout structures, signal routing, power grid, and perform verification.

Skills

Si layout design

Layout verification

DRC/LVS

Problem solving

Project coordination

Education

Bachelor's Degree in Electronics Engineering

Tools

Cadence Virtuoso

Design verification tools

Job description

UST in Malaysia seeks an experienced IC layout engineer to execute high density Si layout designs for EMIB, interposer and test chips. You will create custom IC layouts to specification and run comprehensive verification including DRC/LVS and reliability checks.

The role requires 7+ years of IC layout experience, proficiency with Cadence Virtuoso, and strong problem-solving skills to troubleshoot complex layout issues and optimize flows.