Physical Design Manager

UST; Penang; On-site; MYR 380,000 - 520,000; Full time

Job summary

UST is seeking an experienced Physical Design Manager to lead end-to-end ASIC/SoC implementation in Penang, Malaysia. The role requires 10+ years in physical design and strong leadership to drive floorplanning, placement, CTS, routing, and sign-off.

You will collaborate with RTL, DFT, STA, packaging, and foundry teams, manage schedules, mentor engineers, and enable successful tape-outs across global teams.

Qualifications

• 10+ years of hands-on Physical Design experience in advanced technology nodes.
• Strong expertise in floorplanning, placement, CTS, routing, timing closure, and physical verification.
• Experience with industry-standard EDA tools (ICC2/Fusion Compiler, PrimeTime, Innovus) and sign-off tools.

Responsibilities

• Lead and manage Physical Design activities from floorplanning to tape-out for complex ASIC/SoC projects.
• Drive PPA (Performance, Power, Area) optimization and sign-off closure, including timing, power, IR drop, EM, and physical verification.
• Collaborate with RTL, DFT, STA, Packaging, and Foundry teams to ensure successful project execution.
• Manage project schedules, resource planning, risk assessment, and technical issue resolution.
• Mentor and guide Physical Design engineers, fostering technical excellence and team growth.
• Support customer engagements and cross-site collaboration with global engineering teams.

Skills

Physical Design

ASIC/SoC

Leadership

Team collaboration

Communication

Education

Bachelor's or Master's degree in Electrical/Electronic Engineering or related field

Tools

Synopsys ICC2/Fusion Compiler

PrimeTime

Cadence Innovus

Job description

We are seeking an experienced Physical Design Manager with 10+ years of ASIC/SoC Physical Design experience to lead and drive end-to-end implementation activities for advanced semiconductor products. The ideal candidate will possess strong technical expertise in physical design methodologies, project leadership capabilities, and the ability to collaborate effectively with global teams.

Key Responsibilities

• Lead and manage Physical Design activities from floorplanning to tape-out for complex ASIC/SoC projects.
• Drive PPA (Performance, Power, Area) optimization and sign-off closure, including timing, power, IR drop, EM, and physical verification.
• Collaborate with RTL, DFT, STA, Packaging, and Foundry teams to ensure successful project execution.
• Manage project schedules, resource planning, risk assessment, and technical issue resolution.
• Mentor and guide Physical Design engineers, fostering technical excellence and team growth.
• Support customer engagements and cross-site collaboration with global engineering teams.

Requirements

• Bachelor's or Master's degree in Electrical/Electronic Engineering or related field.
• 10+ years of hands-on Physical Design experience in advanced technology nodes.
• Strong expertise in floorplanning, placement, CTS, routing, timing closure, and physical verification.
• Experience with industry-standard EDA tools such as Synopsys ICC2/Fusion Compiler, PrimeTime, Cadence Innovus, and related sign-off tools.
• Proven leadership experience managing teams and delivering successful tape-outs.
• Excellent communication and stakeholder management skills.