Custom IC Layout Engineer for AI Chips

AdoreSys; Bayan Lepas; On-site; MYR 70,000 - 100,000; Full time

Job summary

AdoreSys is seeking a versatile Custom Layout Engineer to shape the physical implementation of diverse circuitry, including Foundation IP, Analog IP, and RF blocks. You’ll own floorplanning, layout construction, verification, and QA, ensuring on‑time delivery while optimizing Power, Performance & Area (PPA).

Candidates should have 2–7 years in custom IC layout, DRM expertise, and proficiency with Synopsys/Cadence tools. This role welcomes senior candidates as well.

Qualifications

• Bachelor’s degree in Electrical, Electronic, or Materials Science Engineering.
• 2–7 years of hands-on custom IC layout experience with finFET/GAA process nodes.
• Strong understanding of DRM, CMOS tech, and DFM issues for high‑performance layouts.
• Proficient in layout editors (Synopsys/Cadence) and physical verification tools.
• Team player with cross‑site communication and time management.

Responsibilities

• Realize physical implementation including floorplanning, layout construction.
• Perform physical verification and QA flow sign‑off for layouts.
• Provide timely project status updates and mitigate execution risks.
• Collaborate with multi‑functional teams to optimize layout for PPA.

Skills

Layout debugging

Cross‑team collaboration

Time management

Analytical thinking

Education

Bachelor’s in Electrical, Electronic, or Materials Science Eng.

Tools

Synopsys/Cadence layout editor

DRC/LVS/ERC verification tools

Job description

AdoreSys is seeking a versatile Custom Layout Engineer to shape the physical implementation of diverse circuitry, including Foundation IP, Analog IP, and RF blocks. You’ll own floorplanning, layout construction, verification, and QA, ensuring on‑time delivery while optimizing Power, Performance & Area (PPA).

Candidates should have 2–7 years in custom IC layout, DRM expertise, and proficiency with Synopsys/Cadence tools. This role welcomes senior candidates as well.