Senior/lead Analog Layout Design Engineer

UST; Seberang Perai; On-site; MYR 180,000 - 300,000; Full time

Benefits offered by this job

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Job summary

UST in Penang, Malaysia, seeks an experienced Senior IC Layout Engineer to lead analog/mixed-signal layout projects. You will drive layout optimization, floorplanning, and verification, collaborating with circuit designers to meet performance targets.

The role requires 7+ years in layout design, strong proficiency with Cadence Virtuoso and Mentor Graphics, and proven mentoring ability in a cross-functional team. On-site with competitive benefits.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field
• 7+ years of analog/mixed-signal IC layout design experience
• Proficiency with industry-standard EDA tools (Cadence, Mentor Graphics)
• Deep understanding of transistor-level and analog circuit topologies and their layout sensitivities
• Strong problem-solving skills and attention to detail
• Excellent communication and cross-functional collaboration abilities
• Experience mentoring and leading layout teams is a plus

Responsibilities

• Lead and execute layout design of digital, analog, and mixed-signal circuits
• Collaborate with circuit designers to meet requirements and performance targets
• Plan and manage layout schedules, resources, and deliverables
• Perform floorplanning, placement, and routing optimizing area, performance, and manufacturability
• Conduct physical verification (DRC, LVS, ERC) including RV
• Drive design reviews and provide technical mentorship to junior layout engineers
• Interface with foundry partners to ensure compliance with process design rules
• Document design methodology and maintain layout guidelines for future projects

Skills

Layout design

Analog layout

AMS layout

Floorplanning

Placement

Routing

Physical verification

Design reviews

Mentorship

Foundry interface

Documentation

Education

Bachelor's or Master's in Electrical Engineering/Microelectronics

Tools

Cadence Virtuoso

Mentor Graphics

Job description

• Lead and execute layout design of digital. analog and mixed-signal circuit.
• Collaborate closely with circuit designers to understand requirements, constraints, and performance targets.
• Plan and manage layout schedules, resources, and deliverables, ensuring timely completion of projects.
• Perform floorplanning, placement, and routing while optimizing for area, performance, and manufacturability.
• Conduct thorough physical verification such as DRC, LVS, ERC including RV.
• Drive design reviews and provide technical mentorship to junior layout engineers.
• Interface with foundry partners to ensure compliance with process design rules and manufacturing best practices.
• Document design methodology and maintain layout guidelines for future projects.

Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.
• 7+ years of experience in analog/mixed-signal IC layout design.
• Expert proficiency with industry-standard EDA tools (e.g., Cadence Virtuoso, Mentor Graphics).
• Deep understanding of transistor level and analog circuit topologies and their layout sensitivities (matching, parasitics, noise, shielding, etc.).
• Strong problem-solving skills and attention to detail.
• Excellent communication skills and ability to work collaboratively in a cross-functional environment.
• Experience mentoring and leading layout teams is a plus.