Senior IP Verification Engineer (SystemVerilog/UVM)

Lattice Malaysia; Malaysia; On-site; MYR 180,000 - 360,000; Full time

Job summary

Lattice is seeking an experienced Design Verification professional in Malaysia to join our verification team. The role focuses on building scalable SystemVerilog/UVM verification environments for complex IPs, debugging design and verification issues, and collaborating with cross-functional groups to ensure quality across iterations.

Minimum 5+ years in Design Verification with SystemVerilog/UVM is required, along with strong debugging skills and effective communication.

Qualifications

• BS/MS/PhD in Electrical Engineering, Electronics Engineering, Computer Engineering.
• Minimum 5+ years of hands-on Design Verification experience using SystemVerilog and UVM.
• Experience developing constrained-random verification environments for complex digital designs.
• Strong debugging, analytical, and problem-solving skills.
• Excellent communication and teamwork in cross-functional teams.

Responsibilities

• Develop and Review Comprehensive Test Plan based on design specification.
• Develop, and maintain scalable UVM-based constrained-random verification environments for complex IPs.
• Create test cases, sequences, scoreboards, checkers, and assertions based on testplan and drive verification execution from planning through coverage closure and sign-off.
• Analyze failures and perform root-cause debugging of design and verification issues.
• Collaborate closely with design, architecture, system validation, and application teams to resolve issues.
• Contribute to verification methodology improvements, automation initiatives, and best practices across the team.

Education

BS/MS/PhD in Electrical Engineering, Electronics Engineering, Computer Engineering

Tools

SystemVerilog

UVM

Verilog

HDL (Verilog/SystemVerilog)

Python scripting

Job description

Lattice is seeking an experienced Design Verification professional in Malaysia to join our verification team. The role focuses on building scalable SystemVerilog/UVM verification environments for complex IPs, debugging design and verification issues, and collaborating with cross-functional groups to ensure quality across iterations.

Minimum 5+ years in Design Verification with SystemVerilog/UVM is required, along with strong debugging skills and effective communication.