Senior IP DV Engineer | UVM/SystemVerilog Expert

Lattice Semiconductor Corp.; George Town; Sur place; MYR 120 000 - 180 000; Plein temps

Résumé du poste

Lattice Semiconductor Corp. in Penang, Malaysia is seeking a Senior Design Verification Engineer (IP) to join our R&D team.

You will contribute to pre-silicon verification of complex IPs, develop test plans and UVM-based environments, and collaborate with design and system teams to ensure robust silicon. The ideal candidate has 5+ years of hands-on SystemVerilog/UVM experience, strong debugging skills, and familiarity with HDL and high-speed interfaces.

Qualifications

• 5+ years of hands-on Design Verification experience in SystemVerilog and UVM.
• Experience developing constrained-random verification environments for complex IPs.
• Strong debugging, analytical, and problem-solving skills.

Responsabilités

• Develop and review comprehensive test plans based on design specifications.
• Create and maintain scalable UVM-based verification environments for IPs.
• Develop test cases, sequences, scoreboards, checkers and assertions; drive verification from plan to coverage closure.
• Analyze failures and perform root-cause debugging; collaborate with design and system teams to resolve issues.

Connaissances

SystemVerilog

UVM

Constrained-random

Test planning

Debugging

HDL basics

Scripting

Formation

BS/MS/PhD in EE/CE

Outils

UVM framework

Description du poste

Lattice Semiconductor Corp. in Penang, Malaysia is seeking a Senior Design Verification Engineer (IP) to join our R&D team.

You will contribute to pre-silicon verification of complex IPs, develop test plans and UVM-based environments, and collaborate with design and system teams to ensure robust silicon. The ideal candidate has 5+ years of hands-on SystemVerilog/UVM experience, strong debugging skills, and familiarity with HDL and high-speed interfaces.