Senior IP DV Engineer: UVM & SystemVerilog Expert

Lattice Semiconductor; George Town; Presencial; MYR 120.000 - 200.000; Jornada completa

Descripción de la vacante

Lattice Semiconductor is seeking a senior Design Verification Engineer to join the RnD organization. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.

We require hands-on experience with SystemVerilog and UVM, plus the ability to develop constrained-random verification environments for complex IPs. Collaboration across design, validation and applications teams is essential.

Formación

• 5+ years hands-on Design Verification using SV and UVM.
• Experience building constrained-random verification environments.
• Strong debugging, analytical and problem-solving skills.
• Excellent cross-functional communication and teamwork.

Responsabilidades

• Develop and review comprehensive test plans from design specs.
• Create scalable UVM-based verification environments for complex IPs.
• Develop test cases, sequences, scoreboards and assertions.
• Analyze failures and perform root-cause debugging across teams.
• Collaborate with design, architecture, validation and apps teams.
• Contribute to verification methodology improvements and automation.

Conocimientos

Debugging

Analytical thinking

Communication

Teamwork

Educación

BS in Electrical Engineering

MS in Electronics Engineering

PhD in Electrical/Computer Engineering

Herramientas

SystemVerilog

UVM

Python

Tcl

Perl

C/C++

Verilog

FPGA

Descripción del empleo

Lattice Semiconductor is seeking a senior Design Verification Engineer to join the RnD organization. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.

We require hands-on experience with SystemVerilog and UVM, plus the ability to develop constrained-random verification environments for complex IPs. Collaboration across design, validation and applications teams is essential.