Senior FPGA DV Manager - Lead Verification & Innovation

Lattice Semiconductor; Penang; On-site; MYR 120,000 - 190,000; Full time

Job summary

Lattice Semiconductor in Malaysia seeks an experienced FPGA DV engineer to lead verification of complex FPGA/SoC IPs, develop reusable UVM test benches, and drive coverage targets. You will collaborate across design, architecture, software and external IP teams to deliver high-quality silicon for global customers.

The role requires 8+ years in DV and strong SystemVerilog/UVM expertise, with proven leadership and hands-on experience in IP verification, RTL, and testbench development in a

Qualifications

• 8+ years dedicated FPGA/SOC DV experience.
• 5+ years leading a DV team.
• Proven track record from concept to tape-out to silicon bring-up.

Responsibilities

• Verify IP and SOC level designs with reusable UVM test benches.
• Architect and implement coverage-driven verification plans.
• Collaborate with design, architecture, SW, FW and external IP teams.

Skills

FPGA DV

SystemVerilog

UVM methodology

Team leadership

C/C++/Python

IP/SoC verification

Education

BS/MS Electrical/Computer Engineering

Tools

Verilog

UVM TB

Job description

Lattice Semiconductor in Malaysia seeks an experienced FPGA DV engineer to lead verification of complex FPGA/SoC IPs, develop reusable UVM test benches, and drive coverage targets. You will collaborate across design, architecture, software and external IP teams to deliver high-quality silicon for global customers.

The role requires 8+ years in DV and strong SystemVerilog/UVM expertise, with proven leadership and hands-on experience in IP verification, RTL, and testbench development in a