FPGA Design Verification Manager – Lead DV Teams

Lattice Malaysia; Malaysia; On-site; MYR 180,000 - 300,000; Full time

Job summary

Lattice Semiconductor in Malaysia is seeking a senior FPGA/ASIC DV engineer to lead verification efforts within the SOC/FPGA team. You will design, implement, and verify complex IP blocks using UVM, SystemVerilog, and related methodologies, collaborating with design, software, and firmware teams to deliver high-quality silicon.

The role requires extensive DV experience, strong problem-solving skills, and a track record of delivering on tape-out milestones.

Qualifications

• BS or MS Electrical/Computer Engineering, Computer Science, or related field of study
• 8+ years of dedicated/hands-on FPGA/SOC ASIC DV experience
• Advanced knowledge of System Verilog and UVM methodology
• Experience with C/C++, Perl/Python/Tcl for automation of DV tasks
• Experience verifying subsystems like DDR SDRAM Memory, AMBA Interconnect, Ethernet, Video interfaces
• Strong interpersonal and leadership skills for senior/manager roles

Responsibilities

• Understand protocol technologies and how they are implemented in Lattice IPs
• Create coverage driven verification plans from specifications
• Architect UVM-based reusable test benches and integrate VIPs to SOC level
• Work with design, architecture, SW, FW, and external IP teams to verify FPGA designs

Job description

Lattice Semiconductor in Malaysia is seeking a senior FPGA/ASIC DV engineer to lead verification efforts within the SOC/FPGA team. You will design, implement, and verify complex IP blocks using UVM, SystemVerilog, and related methodologies, collaborating with design, software, and firmware teams to deliver high-quality silicon.

The role requires extensive DV experience, strong problem-solving skills, and a track record of delivering on tape-out milestones.