FPGA DV Lead Engineer - Design Verification Manager

Lattice Semiconductor Corp.; Penang; On-site; MYR 260,000 - 380,000; Full time

Job summary

Lattice Semiconductor Corp. in Penang, Malaysia, invites a Manager of Design Eng (Design Verification) to lead a team verifying complex FPGA/SOC IPs, develop reusable UVM test benches, and drive coverage-driven verification.

You will collaborate with architecture, SW, FW, and external IP teams, oversee DV plans from spec to tape-out, and mentor engineers in a fast-paced environment. Candidates should have 8+ years DV experience and proven leadership; extensive SystemVerilog/UVM knowledge is

Qualifications

• BS or MS in Electrical/Computer Engineering, Computer Science, or related field of study.
• 8+ years of dedicated/hands-on FPGA/SOC ASIC DV experience.
• At least 5 years’ experience in leading a DV team to verify complex FPGA/ASIC.
• Advanced knowledge of System Verilog and UVM methodology.
• Experience in using programming languages such as C/C++, Perl/Python/Tcl for automation of DV tasks.
• Experience in verifying Subsystems like DDR SDRAM Memory, AMBA based On-Chip Interconnect, Ethernet, Video (DisplayPort, MIPI, HDMI, SDI), JESD204B, PCIe.
• In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.
• For the manager position, should be a great team leader with strong interpersonal skills, excellent communication and problem-solving skills.

Responsibilities

• Understand details of protocol technologies (DDR SDRAM, AMBA, Ethernet, Video, PCIe) and IP integration.
• Create coverage driven verification plans from specifications and refine to target coverage.
• Architect UVM based highly reusable TBs and integrate multi-instance VIPs to SOC level.
• Collaborate across design, architecture, SW, FW, and external IP teams to verify FPGA designs.

Skills

FPGA DV

ASIC DV

SystemVerilog

UVM

Team leadership

C/C++ automation

Python/Perl/Tcl

DDR/AMBA/PCIe

HW/FW debugging

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Job description

Lattice Semiconductor Corp. in Penang, Malaysia, invites a Manager of Design Eng (Design Verification) to lead a team verifying complex FPGA/SOC IPs, develop reusable UVM test benches, and drive coverage-driven verification.

You will collaborate with architecture, SW, FW, and external IP teams, oversee DV plans from spec to tape-out, and mentor engineers in a fast-paced environment. Candidates should have 8+ years DV experience and proven leadership; extensive SystemVerilog/UVM knowledge is