FPGA DV Engineering Manager

Lattice Semiconductor; Penang; On-site; MYR 180,000 - 300,000; Full time

Job summary

Lattice Semiconductor is seeking a highly skilled FPGA/SoC DV engineer to join its silicon design verification team in Malaysia. You will lead verification activities for complex IP and SOC blocks, develop reusable UVM-based test benches, and drive coverage-driven verification across DDR, PCIe, and AMBA interconnects.

The role requires deep SystemVerilog/UVM expertise, strong scripting in C/C++, Python or Perl, and a track record of delivering full ASIC verification from concept to silicon

Qualifications

• BS or MS in Electrical/Computer Engineering, Computer Science, or related field of study.
• 8+ years of dedicated FPGA/SOC DV experience.
• Proven track record of leading a DV team to verify complex FPGA/ASIC.
• Advanced knowledge of SystemVerilog and UVM methodology.

Responsibilities

• Verify complex IP and SOC blocks using UVM-based test benches.
• Architect reusable TBs and integrate multi-instance VIPs, sub-system test benches and test suites to SOC level.
• Collaborate with design, architecture, SW, FW, and external IP delivery teams to efficiently integrate and verify overall FPGA design.

Skills

SystemVerilog & UVM

DV leadership

Automation scripting

FPGA/ASIC DV

DDR/AMBA/PCIe

Education

BS or MS Electrical/Computer Engineering

Tools

UVM

SystemVerilog

Job description

Lattice Semiconductor is seeking a highly skilled FPGA/SoC DV engineer to join its silicon design verification team in Malaysia. You will lead verification activities for complex IP and SOC blocks, develop reusable UVM-based test benches, and drive coverage-driven verification across DDR, PCIe, and AMBA interconnects.

The role requires deep SystemVerilog/UVM expertise, strong scripting in C/C++, Python or Perl, and a track record of delivering full ASIC verification from concept to silicon