Lead FPGA DV Engineering Manager

Lattice Semiconductor; George Town; On-site; MYR 180,000 - 300,000; Full time

Job summary

Lattice Semiconductor in Penang, Malaysia is seeking an experienced FPGA/SoC DV engineer to join the silicon verification team. You will lead verification of FPGA/ASIC designs, develop reusable UVM-based test benches, and drive coverage targets across IP blocks and subsystems.

You will collaborate with design, architecture, SW, FW, and external IP teams to verify SOC-level functionality, power management, and high-speed interfaces.

Qualifications

• Extensive experience in FPGA/SoC DV and verification environments.
• Strong knowledge of SystemVerilog and UVM methodology.
• Experience with automated DV tasks and test bench development.

Responsibilities

• Lead verification of FPGA/ASIC designs from IP to SOC level.
• Create reusable UVM-based test benches and coverage plans.
• Collaborate with design, architecture, SW, FW, and external IP teams to verify complex protocols.

Skills

SystemVerilog

UVM

FPGA DV

Python

C/C++

DV automation

IP verification

Education

BS/MS in Electrical/Computer Engineering or related field

Tools

UVM TB templates

Verilog/VHDL

Job description

Lattice Semiconductor in Penang, Malaysia is seeking an experienced FPGA/SoC DV engineer to join the silicon verification team. You will lead verification of FPGA/ASIC designs, develop reusable UVM-based test benches, and drive coverage targets across IP blocks and subsystems.

You will collaborate with design, architecture, SW, FW, and external IP teams to verify SOC-level functionality, power management, and high-speed interfaces.