IP Verification Engineer: Formal & UVM Expert

UST; Seberang Perai; On-site; MYR 70,000 - 120,000; Full time

Job summary

UST is seeking an IP-level verification engineer to plan and execute formal and constrained-random verification strategies for block-level IPs in a fast-paced environment.

The role requires 2–6 years of experience in IP block verification, strong SystemVerilog/SVA/UVM expertise, and practical scripting in Python/Tcl/Perl. Collaboration with RTL teams and tool-championing formal verification is essential.

Qualifications

• 2–6 years of industry experience specializing in IP block-level digital design verification.
• Bachelor’s or Master’s degree in Electrical/Computer Engineering or Computer Science.
• Expert command of SystemVerilog, SVA, and UVM architecture (monitors, drivers, scoreboards, sequencers).
• Proficiency in Python, Tcl, or Perl for automated regression runs and log parsing.
• Solid understanding of hardware concepts like CDC, asynchronous FIFOs, arbiters, and pipeline dependencies.

Responsibilities

• Analyze IP specifications and microarchitectural docs to define verification strategies.
• Develop formal properties using SystemVerilog Assertions to prove corner-case logic.
• Build and maintain block-level UVM testbenches to verify deep data paths and traffic patterns.
• Constrain formal tools to avoid state-space explosion and guide convergence.
• Drive block-level sign-off with 100% coverage across code and assertions.
• Collaborate with IP RTL owners to debug failures and refine boundaries for testability.

Skills

SystemVerilog

SVA

UVM

Python

Tcl

Perl

CDC

Clock domain crossing

Arbiters

Pipelining

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Cadence JasperGold

Synopsys VC Formal

Siemens OneSpin

Job description

UST is seeking an IP-level verification engineer to plan and execute formal and constrained-random verification strategies for block-level IPs in a fast-paced environment.

The role requires 2–6 years of experience in IP block verification, strong SystemVerilog/SVA/UVM expertise, and practical scripting in Python/Tcl/Perl. Collaboration with RTL teams and tool-championing formal verification is essential.