IP-Level Verification Architect - Formal & UVM Expert

ThunderSoft; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

ThunderSoft in Malaysia is seeking a Design Verification Engineer – IP-Level & Formal Verification to own block/IP-level verification, formal property verification, and UVM-based verification. You will collaborate with RTL designers to identify issues, develop verification strategies, and drive closure of IP verification milestones.

The ideal candidate has hands-on experience with Synopsys VC Formal and Cadence JasperGold, strong SVA skills, SystemVerilog and UVM, plus scripting in

Qualifications

• Hands-on verification with IP/block-level focus.
• Strong knowledge of SVA and formal verification.
• Experience with UVM-based environments and TCL/Python scripting.

Responsibilities

• Own IP/block-level verification planning and methodology.
• Develop SVA properties and perform formal proof.
• Drive FPV, connectivity checking, register verification, equivalence checking & formal coverage.
• Build and maintain UVM-based verification environments.
• Optimize assumptions and abstractions for proof convergence.
• Analyze counterexamples and debug RTL issues.
• Drive code, functional, assertion and formal coverage closure.
• Automate verification flows and regression using scripting.

Skills

Synopsys VC Formal

Cadence JasperGold

SystemVerilog Assertions

Formal property development

UVM-based verification

SystemVerilog

Scripting (TCL/Python/Perl)

Digital design fundamentals

Job description

ThunderSoft in Malaysia is seeking a Design Verification Engineer – IP-Level & Formal Verification to own block/IP-level verification, formal property verification, and UVM-based verification. You will collaborate with RTL designers to identify issues, develop verification strategies, and drive closure of IP verification milestones.

The ideal candidate has hands-on experience with Synopsys VC Formal and Cadence JasperGold, strong SVA skills, SystemVerilog and UVM, plus scripting in