Design Verification Engineer

ThunderSoft; Penang; On-site; MYR 60,000 - 90,000; Full time

Job summary

ThunderSoft in Penang, Malaysia seeks a Design Verification Engineer – IP-Level & Formal Verification to own block/IP verification, formal properties, and UVM-based verification. You will collaborate with RTL teams to define verification strategies, develop SVA properties, and drive coverage closure.

Requirements include hands-on experience with Synopsys VC Formal or Cadence JasperGold, strong SystemVerilog, UVM, and TCL/Python/Perl scripting.

Qualifications

• Hands-on experience with formal verification methods and property development.
• Strong knowledge of SystemVerilog Assertions (SVA) and formal coverage.
• Proven ability to develop FPV strategies and drive convergence.

Responsibilities

• Own IP/block-level verification planning and methodology.
• Develop SVA properties and perform formal proofs.
• Drive FPV, connectivity, register and equivalence verification.
• Build and maintain UVM-based verification environments.
• Automate verification flows and regression using scripting.

Skills

SystemVerilog

SVA

UVM

Formal verification

TCL/Python/Perl

Digital design fundamentals

Connectivity checking

Register verification

Equivalence checking

FPV

Tools

Synopsys VC Formal

Cadence JasperGold

Job description

Experience: 3–6 Years

About the Role

We are looking for a Design Verification Engineer – IP-Level & Formal Verification to join our semiconductor engineering team and take ownership of block/IP-level verification, formal property verification, and UVM-based verification.

The ideal candidate will have strong hands-on experience with Synopsys VC Formal and/or Cadence JasperGold, combined with solid expertise in SystemVerilog Assertions (SVA), formal property specification, SystemVerilog, and UVM.

You will work closely with RTL designers and verification teams to identify corner-case design issues, develop formal verification strategies, achieve proof convergence, and drive IP/block-level verification closure.

Key Responsibilities:

• Own IP/block-level verification planning and methodology.
• Develop SVA properties and perform formal proof.
• Drive FPV, connectivity, register and equivalence verification.
• Build and maintain UVM-based verification environments.
• Optimize assumptions, constraints and abstractions for proof convergence.
• Analyze counterexamples and debug RTL issues.
• Drive code, functional, assertion and formal coverage closure.
• Automate verification flows and regression using scripting.

Must-Have Skills:

• Hands-on Synopsys VC Formal and/or Cadence JasperGold
• 3 - 6 years of experience in digital design verification for ASICs, SoCs, or IP blocks
• Strong SystemVerilog Assertions (SVA) and formal property development
• Experience in FPV, connectivity checking, register verification, equivalence checking & formal coverage
• Strong SystemVerilog knowledge
• Experience with UVM-based verification
• Proficiency in TCL / Python / Perl scripting
• Strong understanding of CDC, asynchronous FIFO, arbiters, state machines and digital design fundamentals

Good to Have:

• AMBA AXI/AHB/APB or TileLink verification
• Formal scoreboarding / data integrity verification
• Experience combining formal and simulation-based verification