Formal Verification Engineer

UST; Penang; On-site; MYR 120,000 - 160,000; Full time

Job summary

UST is seeking an IP verification engineer in Penang to own block-level verification planning and formal property development. You will build UVM-based testbenches to verify deep data paths and complex traffic patterns, while optimizing proofs to converge without state-space explosion.

The role requires hands-on SystemVerilog, SVA, and UVM experience, plus strong scripting in Python/Tcl/Perl and a solid grasp of CDC concepts and FIFOs. This is a full-time position in Malaysia.

Qualifications

• 2 to 6 years of IP block verification experience.
• Bachelor’s or Master’s degree in Electrical/Computer Engineering or Computer Science.
• Hands-on experience with formal verification tools (JasperGold, VC Formal, OneSpin).
• Expert in SystemVerilog, SVA, and UVM.
• Scripting skills in Python, Tcl, or Perl.
• Solid understanding of CDC, asynchronous FIFOs, arbiters, and pipelines.

Responsibilities

• IP-Level Verification Planning: define verification strategies for IP blocks.
• Formal property development using SystemVerilog Assertions (SVA).
• UVM testbench ownership to verify data paths and traffic patterns.
• Proof convergence optimization to avoid state-space explosion.
• Block-level closure with 100% code, functional, and assertion coverage.
• RTL triage with RTL design owner to debug issues and refine boundaries.

Skills

IP block-level verification

SystemVerilog

SVA

UVM

Python scripting

Tcl scripting

Perl scripting

CDC concepts

Education

Bachelor’s or Master’s degree in Electrical / Computer Engineering or Computer Science

Tools

Cadence JasperGold

Synopsys VC Formal

Siemens OneSpin

Job description

Key Responsibilities

• IP-Level Verification Planning: Analyze IP specifications and microarchitectural documents to define comprehensive verification strategies, mapping out which blocks require formal proofs and which require constrained-random testbenches.
• Formal Property Development: Develop explicit SystemVerilog Assertions (SVA) to mathematically prove corner-case control logic, state machines, and interface protocols within the IP.
• UVM Testbench Ownership: Build, maintain, and run block-level testbenches using SystemVerilog and UVM to verify deep data paths and complex traffic patterns.
• Proof Convergence Optimization: Set up design assumptions, constraints, and custom abstractions to guide formal tools away from state-space explosion and achieve full mathematical convergence.
• Block-Level Closure: Drive block-level sign-off by achieving 100% code coverage, functional coverage, and assertion coverage.
• RTL Triage: Work closely with the IP RTL design owner to debug block-level failures, root-cause design issues, and refine microarchitectural boundaries for better testability.

Required Experience and Technical Skills

• Experience: 2 to 6 years of industry experience specializing in IP block-level digital design verification.
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Formal EDA Tools: Practical experience with commercial formal verification software (e.g., Cadence JasperGold, Synopsys VC Formal, or Siemens OneSpin).
• Languages & Standards: Expert command of SystemVerilog, SVA, and UVM architecture (monitors, drivers, scoreboards, and sequencers).
• Scripting: Proficiency in Python, Tcl, or Perl for managing automated block-level regression runs and parsing logs.
• Technical Fundamentals: Solid understanding of hardware design concepts like clock domain crossing (CDC), asynchronous FIFOs, arbiters, and pipeline dependencies.

Preferred Qualifications (Nice to Have)

• Direct experience writing formal properties for standard IP interfaces like AMBA (AXI, AHB, APB) or tilelink.
• Familiarity with Formal Scoreboarding for data integrity verification.
• Knowledge of power management verification (UPF) at the IP level.