Senior Design Verification Engineer

Oppstar Berhad; Seberang Perai; On-site; MYR 80,000 - 120,000; Full time

Job summary

Oppstar Berhad in Penang seeks a results-driven verification engineer to perform pre-Si verification on FPGA/ASIC designs, define test plans, and develop SystemVerilog/UVM test benches.

You will collaborate with IP architect and design team to ensure high-quality validation, using Cadence, Mentor Graphics or Synopsys tool flows. A strong background in functional verification and IP protocols is essential.

Qualifications

• PhD/MSEE or BSEE with 4+ years of relevant experience.
• Experience in functional verification including test planning and test bench development.
• Proficient with SystemVerilog OVM/UVM and assertion-based verification.
• Familiar with IP protocols (HSST, Ethernet, PCIe, DDR) and FPGA/ARM architectures.
• Hands-on with Cadence, Mentor Graphics or Synopsys tool flows.

Responsibilities

• Perform pre-Si verification on FPGA/ASIC designs.
• Define test plans and develop SystemVerilog/UVM test benches.
• Debug and run regressions to ensure high-quality validation.
• Collaborate with IP architect and design team to improve validation.

Skills

Functional verification

Test planning

Test bench development

Stimulus generation

Reference model

Assertion checkers

Functional coverage

SystemVerilog UVM

Assertion-based verification

Constrained random verification

IP protocols HSST

Ethernet

PCIe

DDR

FPGA

ARM architectures

Cadence

Mentor Graphics

Synopsys

Education

BSEE/MSEE/PhD with 4+ years' relevant experience

Tools

Cadence

Mentor Graphics

Synopsys

Job description

• Perform pre-Si verification on various IP blocks and full-chip of FPGA/ASIC designs.
• The job scope includes test plan definition, SystemVerilog/UVM test bench and content development, debugging and running regression to deliver good-quality design.
• Candidate will work closely with team and interact with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure high quality design validation.

Qualifications

• BSEE/MSEE/PhD with at least 4 years' relevant experience
• Experience in functional verification that may includes test planning, test bench development, stimulus generation, reference model and assertion checkers development and functional coverage.
• Experience with modern verification techniques e.g. SystemVerilog OVM/UVM, assertion-based verification, constrained random verification methodologies.
• Familiar with IP protocols (e.g. HSST, Ethernet, PCIe, DDR), FPGA and/or ARM architectures.
• Hands-on experience in various logic designs and verification tools and flow e.g. from Cadence, Mentor Graphics and/or Synopsys.