Design Verification Engineer (IP Level & Formal Focus)

UST; Seberang Perai; On-site; MYR 70,000 - 120,000; Full time

Job summary

UST is seeking an IP-level verification engineer to plan and execute formal and constrained-random verification strategies for block-level IPs in a fast-paced environment.

The role requires 2–6 years of experience in IP block verification, strong SystemVerilog/SVA/UVM expertise, and practical scripting in Python/Tcl/Perl. Collaboration with RTL teams and tool-championing formal verification is essential.

Qualifications

• 2–6 years of industry experience specializing in IP block-level digital design verification.
• Bachelor’s or Master’s degree in Electrical/Computer Engineering or Computer Science.
• Expert command of SystemVerilog, SVA, and UVM architecture (monitors, drivers, scoreboards, sequencers).
• Proficiency in Python, Tcl, or Perl for automated regression runs and log parsing.
• Solid understanding of hardware concepts like CDC, asynchronous FIFOs, arbiters, and pipeline dependencies.

Responsibilities

• Analyze IP specifications and microarchitectural docs to define verification strategies.
• Develop formal properties using SystemVerilog Assertions to prove corner-case logic.
• Build and maintain block-level UVM testbenches to verify deep data paths and traffic patterns.
• Constrain formal tools to avoid state-space explosion and guide convergence.
• Drive block-level sign-off with 100% coverage across code and assertions.
• Collaborate with IP RTL owners to debug failures and refine boundaries for testability.

Skills

SystemVerilog

SVA

UVM

Python

Tcl

Perl

CDC

Clock domain crossing

Arbiters

Pipelining

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Cadence JasperGold

Synopsys VC Formal

Siemens OneSpin

Job description

• IP-Level Verification Planning: Analyze IP specifications and microarchitectural documents to define comprehensive verification strategies, mapping out which blocks require formal proofs and which require constrained-random testbenches.
• Formal Property Development: Develop explicit SystemVerilog Assertions (SVA) to mathematically prove corner-case control logic, state machines, and interface protocols within the IP.
• UVM Testbench Ownership: Build, maintain, and run block-level testbenches using SystemVerilog and UVM to verify deep data paths and complex traffic patterns.
• Proof Convergence Optimization: Set up design assumptions, constraints, and custom abstractions to guide formal tools away from state-space explosion and achieve full mathematical convergence.
• Block-Level Closure: Drive block-level sign-off by achieving 100% code coverage, functional coverage, and assertion coverage.
• RTL Triage: Work closely with the IP RTL design owner to debug block-level failures, root-cause design issues, and refine microarchitectural boundaries for better testability.

Required Experience and Technical Skills

• Experience: 2 to 6 years of industry experience specializing in IP block-level digital design verification.
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Formal EDA Tools: Practical experience with commercial formal verification software (e.g., Cadence JasperGold, Synopsys VC Formal, or Siemens OneSpin).
• Languages & Standards: Expert command of SystemVerilog, SVA, and UVM architecture (monitors, drivers, scoreboards, and sequencers).
• Scripting: Proficiency in Python, Tcl, or Perl for managing automated block-level regression runs and parsing logs.
• Technical Fundamentals: Solid understanding of hardware design concepts like clock domain crossing (CDC), asynchronous FIFOs, arbiters, and pipeline dependencies.

Preferred Qualifications (Nice to Have)

• Direct experience writing formal properties for standard IP interfaces like AMBA (AXI, AHB, APB) or tilelink.
• Familiarity with Formal Scoreboarding for data integrity verification.
• Knowledge of power management verification (UPF) at the IP level.