Senior Design Verification Engineer-IP-Level & Formal Verification

ThunderSoft; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

ThunderSoft in Malaysia is seeking a Design Verification Engineer – IP-Level & Formal Verification to own block/IP-level verification, formal property verification, and UVM-based verification. You will collaborate with RTL designers to identify issues, develop verification strategies, and drive closure of IP verification milestones.

The ideal candidate has hands-on experience with Synopsys VC Formal and Cadence JasperGold, strong SVA skills, SystemVerilog and UVM, plus scripting in

Qualifications

• Hands-on verification with IP/block-level focus.
• Strong knowledge of SVA and formal verification.
• Experience with UVM-based environments and TCL/Python scripting.

Responsibilities

• Own IP/block-level verification planning and methodology.
• Develop SVA properties and perform formal proof.
• Drive FPV, connectivity checking, register verification, equivalence checking & formal coverage.
• Build and maintain UVM-based verification environments.
• Optimize assumptions and abstractions for proof convergence.
• Analyze counterexamples and debug RTL issues.
• Drive code, functional, assertion and formal coverage closure.
• Automate verification flows and regression using scripting.

Skills

Synopsys VC Formal

Cadence JasperGold

SystemVerilog Assertions

Formal property development

UVM-based verification

SystemVerilog

Scripting (TCL/Python/Perl)

Digital design fundamentals

Job description

We are looking for a Design Verification Engineer – IP-Level & Formal Verification to join our semiconductor engineering team and take ownership of block/IP-level verification, formal property verification, and UVM-based verification.

The ideal candidate will have strong hands‑on experience with Synopsys VC Formal and/or Cadence JasperGold, combined with solid expertise in SystemVerilog Assertions (SVA), formal property specification, SystemVerilog, and UVM.

You will work closely with RTL designers and verification teams to identify corner‑case design issues, develop formal verification strategies, achieve proof convergence, and drive IP/block-level verification closure.

Key Responsibilities

• Own IP/block-level verification planning and methodology.
• Develop SVA properties and perform formal proof.
• Drive FPV, connectivity, register and equivalence verification.
• Build and maintain UVM-based verification environments.
• Optimize assumptions, constraints and abstractions for proof convergence.
• Analyze counterexamples and debug RTL issues.
• Drive code, functional, assertion and formal coverage closure.
• Automate verification flows and regression using scripting.

Must-Have Skills

• Hands‑on Synopsys VC Formal and/or Cadence JasperGold
• 3 - 6 years of experience in digital design verification for ASICs, SoCs, or IP blocks
• Strong SystemVerilog Assertions (SVA) and formal property development
• Experience in FPV, connectivity checking, register verification, equivalence checking & formal coverage
• Strong SystemVerilog knowledge
• Experience with UVM-based verification
• Proficiency in TCL / Python / Perl scripting
• Strong understanding of CDC, asynchronous FIFO, arbiters, state machines and digital design fundamentals

Good to Have

• AMBA AXI/AHB/APB or TileLink verification
• Formal scoreboarding / data integrity verification
• UPF / power-management verification
• Experience combining formal and simulation-based verification