Design Verification Engineer

UST Malaysia; Penang; On-site; MYR 60,000 - 100,000; Full time

Job summary

UST Malaysia in Penang is seeking a Digital IP Verification Engineer to join a team verifying complex IPs and driving milestones. You will build verification environments and UVM/OVM testbenches based on chip requirements, and work across RTL, power-aware, and gate-level verification.

The ideal candidate holds a Bachelor’s degree in Electrical/Electronic Engineering or related and has 1–6 years of hands-on SV/UVM verification experience, with knowledge of ASIC concepts and scripting skills a

Qualifications

• Bachelor’s degree in Electrical/Electronic Engineering or related.
• 1–6 years of hands-on experience in digital IP verification using SV/UVM or similar methodologies.
• Solid knowledge of ASIC verification concepts.
• Willing to relocate and work in Penang, Malaysia.

Responsibilities

• Be part of a team verifying complex IPs and driving them to closure against challenging milestones.
• Build verification environments and UVM/OVM testbenches based on chip requirements.
• Work across RTL, power-aware, and gate-level verification.

Skills

Digital IP verification

SV/UVM

ASIC verification concepts

Perl/Python scripting

Education

Bachelor’s degree in Electrical/Electronic Engineering or related

Tools

Perl/Python

Job description

• Be part of a team verifying complex IPs and driving them to closure against challenging milestones.
• Build verification environments and UVM/OVM testbenches based on chip requirements.
• Work across RTL, power-aware, and gate-level verification.

Requirement:

• Bachelor’s degree (or higher) in Electrical/Electronic Engineering or related.
• 1-6 years of hands‑on experience in digital IP verification using SV/UVM or similar methodologies.
• Solid knowledge of ASIC verification concepts.
• Bonus if you’ve dabbled in scripting (Perl/Python) or have database know‑how.
• Willing to relocate and work in Penang, Malaysia