Senior Design Verification Engineer

Private Advertiser; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Private Advertiser in Malaysia seeks a senior verification engineer to perform pre-Si verification on FPGA/ASIC designs. You will define test plans, develop SystemVerilog UVM test benches, and debug regressions to ensure high-quality designs.

Collaborating with IP architects and design teams, you will implement coverage, assertions, and constrained-random verification, working with Cadence, Mentor Graphics or Synopsys tools.

Qualifications

• Experience in thorough functional verification planning and test bench development.
• Knowledge of HSST, Ethernet, PCIe, DDR IP protocol suites.
• Familiar with modern verification techniques and coverage-driven verification.
• Hands-on with EDA tools Cadence, Mentor Graphics or Synopsys.

Responsibilities

• Perform pre-Si verification on FPGA/ASIC designs.
• Define test plans and develop SystemVerilog/UVM test benches.
• Debug and run regression to deliver high-quality designs.
• Collaborate with IP architects and design teams.

Skills

SystemVerilog

UVM

Assertion-based verification

Constrained random verification

Functional verification

Test planning

HDL verification

Education

BSEE/MSEE/PhD with 4+ years

Tools

Cadence

Mentor Graphics

Synopsys

Job description

Perform pre-Si verification on various IP blocks and full-chip of FPGA/ASIC designs.

The job scope includes test plan definition, SystemVerilog/UVM test bench and content development, debugging and running regression to deliver good-quality design.

Candidate will work closely with team and interact with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure high quality design validation..

Qualifications:

BSEE/MSEE/PhD with at least 4 years' relevant experience

Experience in functional verification that may includes test planning, test bench development, stimulus generation, reference model and assertion checkers development and functional coverage.

Experience with modern verification techniques e.g. SystemVerilog OVM/UVM, assertion-based verification, constrained random verification methodologies.

Familiar with IP protocols (e.g. HSST, Ethernet, PCIe, DDR), FPGA and/or ARM architectures.

Hands-on experience in various logic designs and verification tools and flow e.g. from Cadence, Mentor Graphics and/or Synopsys.