IP-Level Verification Engineer - Formal & UVM FPV

ThunderSoft; Penang; On-site; MYR 60,000 - 90,000; Full time

Job summary

ThunderSoft in Penang, Malaysia seeks a Design Verification Engineer – IP-Level & Formal Verification to own block/IP verification, formal properties, and UVM-based verification. You will collaborate with RTL teams to define verification strategies, develop SVA properties, and drive coverage closure.

Requirements include hands-on experience with Synopsys VC Formal or Cadence JasperGold, strong SystemVerilog, UVM, and TCL/Python/Perl scripting.

Qualifications

• Hands-on experience with formal verification methods and property development.
• Strong knowledge of SystemVerilog Assertions (SVA) and formal coverage.
• Proven ability to develop FPV strategies and drive convergence.

Responsibilities

• Own IP/block-level verification planning and methodology.
• Develop SVA properties and perform formal proofs.
• Drive FPV, connectivity, register and equivalence verification.
• Build and maintain UVM-based verification environments.
• Automate verification flows and regression using scripting.

Skills

SystemVerilog

SVA

UVM

Formal verification

TCL/Python/Perl

Digital design fundamentals

Connectivity checking

Register verification

Equivalence checking

FPV

Tools

Synopsys VC Formal

Cadence JasperGold

Job description

ThunderSoft in Penang, Malaysia seeks a Design Verification Engineer – IP-Level & Formal Verification to own block/IP verification, formal properties, and UVM-based verification. You will collaborate with RTL teams to define verification strategies, develop SVA properties, and drive coverage closure.

Requirements include hands-on experience with Synopsys VC Formal or Cadence JasperGold, strong SystemVerilog, UVM, and TCL/Python/Perl scripting.