Senior Design Verification Engineer

AllwaysFirst; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

AllwaysFirst in Penang, Malaysia, is expanding its semiconductor engineering team and seeks a Design Verification Engineer with 5+ years of RTL verification experience to support pre-silicon IP validation.

You will work with UVM-based verification, SystemVerilog, functional coverage, assertions, and FPV, developing testbenches and debugging alongside RTL designers to deliver high-quality IP. This role offers a challenging environment and opportunities for innovation in verification methodologies.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or related field.
• Minimum 5 years of semiconductor design verification experience.
• Strong RTL verification and debugging skills, plus pre-silicon methodologies.

Responsibilities

• Develop and maintain UVM-based verification environments for IP designs.
• Create detailed verification test plans from design specs and docs.
• Develop constrained-random testbenches, scoreboards, monitors, and other components.
• Perform coverage-driven verification including functional, code, and assertion coverage.
• Drive coverage closure by identifying gaps and improving tests.
• Execute gate-level simulations to validate timing, resets, and power-up after synthesis.
• Apply FPV to verify critical properties and identify corner cases.
• Debug simulation failures and collaborate with RTL designers to resolve issues.
• Develop SystemVerilog Assertions where required.
• Document results, metrics, and regression summaries for QA.

Skills

UVM verification

SystemVerilog

RTL verification

Functional coverage

Assertions

Debugging

FPV

Testbench development

SystemVerilog Assertions

Education

Electrical Engineering degree

Tools

EDA tools

Simulation tools

Gate-level simulations

Job description

Our client is expanding its semiconductor engineering team and is looking for experienced Design Verification Engineers to support RTL verification and pre-silicon validation of IP designs.

This role will focus on UVM-based verification, SystemVerilog, functional coverage, debugging, assertions, and verification methodology development. The position level will be determined based on the candidate's overall experience and technical expertise.

Key responsibilities

• Develop and maintain UVM-based verification environments for IP designs.
• Create detailed verification test plans based on design specifications, architecture documents, and use cases.
• Develop constrained-random testbenches, scoreboards, monitors, and other verification components.
• Perform coverage-driven verification, including functional, code, and assertion coverage.
• Drive coverage closure by identifying verification gaps and improving test scenarios.
• Execute gate-level simulations to validate timing, reset sequences, and power-up behavior after synthesis.
• Apply Formal Property Verification (FPV) to verify critical design properties and identify corner-case issues.
• Debug simulation failures and work closely with RTL designers to resolve issues.
• Develop and maintain SystemVerilog Assertions (SVA) where required.
• Document verification results, coverage metrics, and regression summaries for traceability and quality assurance.
• Contribute to the development and improvement of verification methodologies.

Requirements

• Bachelor's or Master's degree in Electrical Engineering or a related field.
• 5+ years of experience in semiconductor Design Verification.
• Strong experience in RTL verification and debugging.
• Solid knowledge of pre-silicon verification methodologies.
• Hands-on experience with UVM and SystemVerilog.
• Experience with industry-standard EDA tools.
• Strong analytical, troubleshooting, and problem-solving skills.
• Experience in validation and functional verification.
• Certifications related to validation or verification are a plus.

This opportunity is open to applicants of all nationalities willing to relocate to Penang, Malaysia.