Senior IP/SoC Verification Engineer - SystemVerilog/UVM

Private Advertiser; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Private Advertiser in Malaysia seeks a senior verification engineer to perform pre-Si verification on FPGA/ASIC designs. You will define test plans, develop SystemVerilog UVM test benches, and debug regressions to ensure high-quality designs.

Collaborating with IP architects and design teams, you will implement coverage, assertions, and constrained-random verification, working with Cadence, Mentor Graphics or Synopsys tools.

Qualifications

• Experience in thorough functional verification planning and test bench development.
• Knowledge of HSST, Ethernet, PCIe, DDR IP protocol suites.
• Familiar with modern verification techniques and coverage-driven verification.
• Hands-on with EDA tools Cadence, Mentor Graphics or Synopsys.

Responsibilities

• Perform pre-Si verification on FPGA/ASIC designs.
• Define test plans and develop SystemVerilog/UVM test benches.
• Debug and run regression to deliver high-quality designs.
• Collaborate with IP architects and design teams.

Skills

SystemVerilog

UVM

Assertion-based verification

Constrained random verification

Functional verification

Test planning

HDL verification

Education

BSEE/MSEE/PhD with 4+ years

Tools

Cadence

Mentor Graphics

Synopsys

Job description

Private Advertiser in Malaysia seeks a senior verification engineer to perform pre-Si verification on FPGA/ASIC designs. You will define test plans, develop SystemVerilog UVM test benches, and debug regressions to ensure high-quality designs.

Collaborating with IP architects and design teams, you will implement coverage, assertions, and constrained-random verification, working with Cadence, Mentor Graphics or Synopsys tools.