Formal Verification Engineer: IP-Level, SVA & UVM Expert

UST; Penang; On-site; MYR 120,000 - 160,000; Full time

Job summary

UST is seeking an IP verification engineer in Penang to own block-level verification planning and formal property development. You will build UVM-based testbenches to verify deep data paths and complex traffic patterns, while optimizing proofs to converge without state-space explosion.

The role requires hands-on SystemVerilog, SVA, and UVM experience, plus strong scripting in Python/Tcl/Perl and a solid grasp of CDC concepts and FIFOs. This is a full-time position in Malaysia.

Qualifications

• 2 to 6 years of IP block verification experience.
• Bachelor’s or Master’s degree in Electrical/Computer Engineering or Computer Science.
• Hands-on experience with formal verification tools (JasperGold, VC Formal, OneSpin).
• Expert in SystemVerilog, SVA, and UVM.
• Scripting skills in Python, Tcl, or Perl.
• Solid understanding of CDC, asynchronous FIFOs, arbiters, and pipelines.

Responsibilities

• IP-Level Verification Planning: define verification strategies for IP blocks.
• Formal property development using SystemVerilog Assertions (SVA).
• UVM testbench ownership to verify data paths and traffic patterns.
• Proof convergence optimization to avoid state-space explosion.
• Block-level closure with 100% code, functional, and assertion coverage.
• RTL triage with RTL design owner to debug issues and refine boundaries.

Skills

IP block-level verification

SystemVerilog

SVA

UVM

Python scripting

Tcl scripting

Perl scripting

CDC concepts

Education

Bachelor’s or Master’s degree in Electrical / Computer Engineering or Computer Science

Tools

Cadence JasperGold

Synopsys VC Formal

Siemens OneSpin

Job description

UST is seeking an IP verification engineer in Penang to own block-level verification planning and formal property development. You will build UVM-based testbenches to verify deep data paths and complex traffic patterns, while optimizing proofs to converge without state-space explosion.

The role requires hands-on SystemVerilog, SVA, and UVM experience, plus strong scripting in Python/Tcl/Perl and a solid grasp of CDC concepts and FIFOs. This is a full-time position in Malaysia.