FPGA Verification Engineer - SystemVerilog/UVM Expert

754 Altera Semiconductor Technology (M) Sdn. Bhd.; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera is seeking a highly motivated FPGA Silicon Design Verification Engineer to join our hardware development team in Penang, Malaysia. You will verify FPGA IP blocks, subsystems, and SoC designs using SystemVerilog/UVM, ABV, and constrained-random methods, collaborating with RTL, firmware, and validation teams.

The role emphasizes coverage-driven verification, debugging, and readiness for tape-out and post-silicon support.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 3+ years of experience in digital design verification for FPGA or ASIC products.
• Strong expertise in SystemVerilog UVM ABV constrained-random verification methodologies.
• Solid understanding of digital design fundamentals, including Clock domain crossings (CDC), Reset synchronization, Pipelines, State machines, Memory architectures.
• Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, Siemens QuestaSim.
• Experience developing verification components, scoreboards, monitors, agents, and coverage models.
• Strong debugging skills using waveform viewers and simulation tools.
• Proficiency with scripting languages such as Python, Perl, Tcl, or Shell scripting.
• Experience with version control systems such as Git.

Responsibilities

• Develop and execute comprehensive verification plans based on architecture and design specifications.
• Design, implement, and maintain reusable SystemVerilog/UVM verification environments, testbenches, sequences, and scoreboards.
• Create directed and constrained-random tests to verify FPGA designs.
• Define and track verification metrics, including functional coverage, code coverage, and assertion coverage.
• Develop SystemVerilog Assertions (SVA) to validate design behavior and identify corner-case issues.
• Perform debug and root-cause analysis of design failures using simulation, emulation, waveform analysis, and protocol analyzers.
• Collaborate closely with RTL designers, architects, and firmware teams to resolve functional and performance issues.
• Participate in design reviews, verification reviews, and project milestone assessments.
• Drive verification closure and ensure quality signoff before tape-out or FPGA release.
• Support post-silicon bring-up and validation activities as needed.
• Contribute to verification methodology improvements, automation, and regression infrastructure.

Skills

SystemVerilog

UVM

SVA

Functional Coverage

Regression Automation

Python

Perl

Tcl

Git

Education

Bachelor's or Master's in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Synopsys VCS

Cadence Xcelium

Siemens QuestaSim

Job description

Altera is seeking a highly motivated FPGA Silicon Design Verification Engineer to join our hardware development team in Penang, Malaysia. You will verify FPGA IP blocks, subsystems, and SoC designs using SystemVerilog/UVM, ABV, and constrained-random methods, collaborating with RTL, firmware, and validation teams.

The role emphasizes coverage-driven verification, debugging, and readiness for tape-out and post-silicon support.