Design Verification Engineer — Pre-Silicon & UVM Expert

LATTICE SEMICONDUCTOR MALAYSIA SDN. BHD.; Penang; Sur place; MYR 67 000 - 112 000; Plein temps

Résumé du poste

Lattice Semiconductor Malaysia is seeking a Design Verification Engineer to join the R&D organization in Malaysia. This role offers the opportunity to work on pre-silicon verification, contribute to verification methodologies, and grow within a dynamic team.

Applicants should have hands-on experience with HDL (Verilog/SystemVerilog), UVM/OVM, and constrained-random verification, and be proficient in programming languages like C/C++ or Python.

Qualifications

• BS/MS/PhD in Electronics or Computer Engineering.
• Independent and self-motivated, capable of executing under dynamic environment and uncertainties.
• Experience with SystemVerilog/UVM is required.

Responsabilités

• Develop and Review Test Plan based on design specification.
• Develop constrained-Random verification environment for complex DUT.
• Implement coverage metrics using cover point and assertion.
• Create and debug tests for DUT.
• Resolve bugs with remote designers.

Connaissances

Test planning

Constrained-Random verification

UVM/OVM

HDL (Verilog,SystemVerilog)

C/C++,Python

Strong communication

Analytical skills

Formation

BS/MS/PhD in Electronics or Computer Engineering

Outils

Verilog

SystemVerilog

UVM

OVM

Python

Perl

TCL

Description du poste

Lattice Semiconductor Malaysia is seeking a Design Verification Engineer to join the R&D organization in Malaysia. This role offers the opportunity to work on pre-silicon verification, contribute to verification methodologies, and grow within a dynamic team.

Applicants should have hands-on experience with HDL (Verilog/SystemVerilog), UVM/OVM, and constrained-random verification, and be proficient in programming languages like C/C++ or Python.