Design Verification Engineer - Pre-Silicon UVM Expert

Lattice Semiconductor; Penang; On-site; MYR 120,000 - 190,000; Full time

Job summary

Lattice Semiconductor is seeking a Design Verification Engineer to join its RnD organization in Malaysia. This role offers the chance to contribute to pre-silicon verification, develop verification environments, and advance coverage metrics within a dynamic team.

The engineer will work on Verilog/SystemVerilog designs, FPGA-related tasks, and collaborate with cross-functional teams to deliver high-quality silicon solutions.

Qualifications

• BS/MS/PhD in Electronics or Computer Engineering with SV/UVM experience
• 2+ years of SystemVerilog/UVM experience
• Strong communication and analytical skills

Responsibilities

• Develop and review test plans based on design specification.
• Create constrained-random verification environments for complex DUTs.
• Implement coverage metrics using cover points and assertions.
• Create and debug tests for DUTs.
• Collaborate with remote designers to resolve issues.

Skills

Test plan development

Constrained-Random verification

UVM/OVM

Verilog/SystemVerilog

FPGA experience

C/C++/Python

RTL debugging

Testbench creation

Remote collaboration

HDL knowledge

Education

Electronics or Computer Eng (BS/MS/PhD)

Tools

Remote collaboration

Job description

Lattice Semiconductor is seeking a Design Verification Engineer to join its RnD organization in Malaysia. This role offers the chance to contribute to pre-silicon verification, develop verification environments, and advance coverage metrics within a dynamic team.

The engineer will work on Verilog/SystemVerilog designs, FPGA-related tasks, and collaborate with cross-functional teams to deliver high-quality silicon solutions.