Senior Principal Memory Layout Architect

Micron Technology, Inc.; Tlaquepaque; Híbrido; MXN 1.800.000 - 3.000.000; Jornada completa

Descripción de la vacante

Micron Technology, Inc. in Jalisco is seeking a Lead Principal Engineer to drive layout design for advanced memory products.

You will lead physical implementation from schematics to manufacturable layouts, collaborating with circuit designers, CAD experts, and product teams to meet stringent PPA and reliability targets. You will develop hierarchical analog/digital memory layouts, optimize for die size, timing, and power, and own tapeout readiness through verification, ECOs, and cross-team

Formación

• 10+ years in the Semiconductor industry.
• Strong CMOS/layout knowledge and experience with IC layout.
• Hands-on with layout and physical verification tools.
• Experience leading tapeouts and reliability checks.
• Proficient in scripting/automation to improve layout efficiency.

Responsabilidades

• Lead the layout build and physical realization of new memory products.
• Interpret device and circuit specs to implement layout meeting PPA targets.
• Develop hierarchical layouts for analog, digital, and memory circuitry using EDA tools.
• Build block and top-level floorplans optimizing placement, routing, power, manufacturability.
• Optimize layout for die size, matching, noise, and timing.
• Produce layout collateral and documentation for cross-team integration.
• Run and debug physical verification flows and ensure closure.
• Resolve layout issues related to signal integrity, coupling, and power integrity.
• Lead resource planning and tapeout schedules across blocks; coordinate ECOs.

Conocimientos

Semiconductor industry experience

CMOS/layout understanding

IC layout

Scripting/automation

Tapeout leadership

Educación

Bachelor's degree in Electrical/Computer Engineering

Master's or PhD in Electrical/Computer Engineering or related field

Herramientas

IC layout tools

Physical verification tools

Descripción del empleo

Micron Technology, Inc. in Jalisco is seeking a Lead Principal Engineer to drive layout design for advanced memory products.

You will lead physical implementation from schematics to manufacturable layouts, collaborating with circuit designers, CAD experts, and product teams to meet stringent PPA and reliability targets. You will develop hierarchical analog/digital memory layouts, optimize for die size, timing, and power, and own tapeout readiness through verification, ECOs, and cross-team