DRAM Layout Engineer Intern: Design, Verify & Innovate

Micron Technology, Inc; Tlaquepaque; On-site; MXN 134,000 - 201,000; Part time

Job summary

Micron Technology, Inc is seeking an Intern Senior- Non Mfg. in Jalisco to contribute to analog and digital layout design and verification.

You will work with Cadence tools, collaborate with design engineers on floor plans, and learn verification protocols. Applicants are pursuing a bachelor’s degree related to electrical or electronics engineering with interest in semiconductor memory technologies and Linux scripting.

Qualifications

• Pursuing a bachelor’s degree in a related field with coursework in microelectronics or VLSI.
• Fundamental CMOS concepts and layout principles.
• Basic problem-solving and teamwork abilities.

Responsibilities

• Design and verify analog and digital layouts at all levels.
• Use Cadence and Calibre or similar tools for layout tasks.
• Collaborate with design engineers for floor planning and layout.
• Understand verification protocols and apply layout techniques.
• Support layout methods for pitch, array and peripheral circuits.

Skills

Analog Layout

Digital Layout

Cadence

Python

Linux

Scripting

Education

Bachelor's degree (last 2 semesters) in Electrical Engineering or related

Tools

Cadence Virtuoso

IC Compiler II

Fusion Compiler

Synopsys IC Compiler

Job description

Micron Technology, Inc is seeking an Intern Senior- Non Mfg. in Jalisco to contribute to analog and digital layout design and verification.

You will work with Cadence tools, collaborate with design engineers on floor plans, and learn verification protocols. Applicants are pursuing a bachelor’s degree related to electrical or electronics engineering with interest in semiconductor memory technologies and Linux scripting.