Senior HBM Layout Engineer for AI & HPC Projects

Micron Technology; Región Centro; On-site; MXN 600,000 - 900,000; Full time

Job summary

Micron Technology, Inc. in Guadalajara, Mexico, is seeking a Layout Design Engineer to contribute to the High Bandwidth Memory (HBM) team.

You will design analog/mixed-signal blocks and lead layout planning for multi-project environments, collaborating with global teams to meet schedules and quality targets. The ideal candidate has 5+ years in analog/custom layout, experience with CMOS processes, and proficiency in Cadence VLE/VXL and Calibre DRC/LVS.

Qualifications

• 5+ years of experience in analog/custom layout design in advanced CMOS process.
• BE or MTech in Electronic/VLSI Engineering, or related.
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Hands-on experience in creating layouts for critical blocks such as sensors, PLLs, ADCs, DACs, and more.

Responsibilities

• Design and development of analog, mixed-signal, and custom digital blocks.
• Perform layout verification like LVS/DRC/Antenna, quality checks and documentation.
• Ensure on-time delivery of block-level layouts with quality targets.
• Lead planning, area/time estimation, scheduling, and execution across projects.

Skills

Analog layout design

CMOS process knowledge

High-level integration

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Job description

Micron Technology, Inc. in Guadalajara, Mexico, is seeking a Layout Design Engineer to contribute to the High Bandwidth Memory (HBM) team.

You will design analog/mixed-signal blocks and lead layout planning for multi-project environments, collaborating with global teams to meet schedules and quality targets. The ideal candidate has 5+ years in analog/custom layout, experience with CMOS processes, and proficiency in Cadence VLE/VXL and Calibre DRC/LVS.