HBM Layout Design Engineer for AI & HPC – Guadalajara

Micron; Región Centro; On-site; MXN 420,000 - 700,000; Full time

Job summary

Micron Technology in Guadalajara, Mexico, is seeking a Layout Design Engineer for the HBM team to craft IC layouts for high-performance memory solutions with attention to performance, power, area, and verification results. You will work with global teams on multiple projects and contribute to AI and HPC applications.

Candidates should have recent graduates with strong circuit knowledge and experience with layout tools, plus good English communication and a drive to learn advanced semiconductor

Qualifications

• Bachelor's, master's, or PhD in Electronics, Mechatronics, Robotics, Nanotechnology, or related field.
• Graduation from the program within the past two years.
• Strong understanding of electronic circuits and simulation/design tools.
• Conversational English proficiency.
• Interest in semiconductor technology and willingness to learn.

Responsibilities

• Craft and develop IC layouts for leaf cells, standard cells, and sub-blocks with focus on performance, power, area.
• Interpret DRC/LVS and other physical verification results to support layouts.
• Apply a systematic, detail-focused approach to problem-solving and verification.
• Collaborate with internal teams across global locations to drive layout projects.
• Continue to learn and develop semiconductor design skills for innovative HBM solutions.

Skills

Circuit concepts

Circuit simulation

Communication

Problem solving

English proficiency

Education

Bachelor's/Master's/PhD in Electronics or related

Tools

Cadence VLE/VXL

Calibre DRC/LVS

Mentor Graphics

Python

C++

Job description

Micron Technology in Guadalajara, Mexico, is seeking a Layout Design Engineer for the HBM team to craft IC layouts for high-performance memory solutions with attention to performance, power, area, and verification results. You will work with global teams on multiple projects and contribute to AI and HPC applications.

Candidates should have recent graduates with strong circuit knowledge and experience with layout tools, plus good English communication and a drive to learn advanced semiconductor