HBM IC Layout Design Engineer – AI/HPC Focus

Micron Technology, Inc.; Región Centro; On-site; MXN 650,000 - 900,000; Full time

Job summary

Micron Technology, Inc. in Guadalajara, Mexico, is seeking a Layout Design Engineer to craft IC layouts for leaf and standard cells and sub-blocks, optimizing performance, power, and area for High Bandwidth Memory projects.

You will interpret DRC/LVS results, collaborate with global teams, and apply a meticulous approach to verification. Recent graduates with related degrees and strong English are encouraged to apply.

Qualifications

• Bachelor’s, master’s, or PhD in Electronics, Mechatronics, Robotics Engineering, Nanotechnology, or related field.
• Graduation from a bachelor’s, master’s, or PhD program within the past two years.
• Strong understanding of electronic circuit concepts and proficiency in electronic circuit simulation or design tools.

Responsibilities

• Craft and develop IC layouts for leaf cells, standard cells, and sub-blocks, with attention to performance, power, area, capacitance, and design efficiency.
• Interpret DRC, LVS, and other physical verification results to support accurate custom layouts.
• Apply a systematic, detail-focused approach to problem-solving and physical verification while planning work efficiently.
• Collaborate with internal engineering teams across global locations to drive successful layout projects.
• Continue to learn and develop semiconductor design skills while contributing to innovative HBM solutions.

Skills

Electronic circuit concepts

Circuit simulation tools

English proficiency

Education

Bachelor’s in Electronics, Mechatronics, Robotics Engineering, Nanotechnology, or related field

Master’s in Electronics, Mechatronics, Robotics Engineering, Nanotechnology, or related field

PhD in Electronics, Mechatronics, Robotics Engineering, Nanotechnology, or related field

Tools

Cadence VLE/VXL

Siemens/Mentor Calibre DRC/LVS

Job description

Micron Technology, Inc. in Guadalajara, Mexico, is seeking a Layout Design Engineer to craft IC layouts for leaf and standard cells and sub-blocks, optimizing performance, power, and area for High Bandwidth Memory projects.

You will interpret DRC/LVS results, collaborate with global teams, and apply a meticulous approach to verification. Recent graduates with related degrees and strong English are encouraged to apply.