DRAM IP Layout Intern: Design & Automation

Micron Technology, Inc; Tlaquepaque; Presencial; MXN 89 000 - 156 000; Tempo parcial

Vantagens oferecidas por esta oferta de emprego

Relocation TBD

Resumo da oferta

Micron Technology, Inc in Mexico is seeking a Layout Design Engineering Intern to contribute to the development and verification of IP layout cells used in memory products. You will work with experienced layout engineers on floorplanning, placement, routing, and physical verification.

You will also explore automation via scripting and AI-supported development to improve productivity and design quality, with opportunities to learn EDA tools such as Cadence or Synopsys.

Qualificações

• Currently pursuing a Bachelor's degree in a relevant engineering field.
• Expected graduation December 2027.
• Experience with at least one scripting language (Python, Perl).
• Strong time management and communication skills.

Responsabilidades

• Develop the layout of selected IP layout cells under guidance of experienced engineers.
• Perform DRC and LVS verification and document findings.
• Create technical reports summarizing design work and verification results.
• Design and implement a SKILL-based automation solution to improve layout processes.
• Support engineering activities through AI-assisted development methodologies.

Conhecimentos

Python scripting

Communication

Time management

Perl scripting

Formação académica

Bachelor's degree in Electrical/ Electronics/ Mechatronics/ Robotics/ Nanotechnology/ Computer Engineering

Ferramentas

Cadence

Synopsys

Descrição da oferta de emprego

Micron Technology, Inc in Mexico is seeking a Layout Design Engineering Intern to contribute to the development and verification of IP layout cells used in memory products. You will work with experienced layout engineers on floorplanning, placement, routing, and physical verification.

You will also explore automation via scripting and AI-supported development to improve productivity and design quality, with opportunities to learn EDA tools such as Cadence or Synopsys.