DRAM IP Development Layout (Internship)

Micron Technology, Inc; Tlaquepaque; Presencial; MXN 89.000 - 156.000; A tiempo parcial

Ventajas ofrecidas por este puesto de trabajo

Relocation TBD

Descripción de la vacante

Micron Technology, Inc in Mexico is seeking a Layout Design Engineering Intern to contribute to the development and verification of IP layout cells used in memory products. You will work with experienced layout engineers on floorplanning, placement, routing, and physical verification.

You will also explore automation via scripting and AI-supported development to improve productivity and design quality, with opportunities to learn EDA tools such as Cadence or Synopsys.

Formación

• Currently pursuing a Bachelor's degree in a relevant engineering field.
• Expected graduation December 2027.
• Experience with at least one scripting language (Python, Perl).
• Strong time management and communication skills.

Responsabilidades

• Develop the layout of selected IP layout cells under guidance of experienced engineers.
• Perform DRC and LVS verification and document findings.
• Create technical reports summarizing design work and verification results.
• Design and implement a SKILL-based automation solution to improve layout processes.
• Support engineering activities through AI-assisted development methodologies.

Conocimientos

Python scripting

Communication

Time management

Perl scripting

Educación

Bachelor's degree in Electrical/ Electronics/ Mechatronics/ Robotics/ Nanotechnology/ Computer Engineering

Herramientas

Cadence

Synopsys

Descripción del empleo

Req ID:

JR108219 DRAM IP Development Layout (Internship)

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

SUMMARY:

At Micron, we are transforming how the world uses information to enrich life for all. As a Layout Design Engineering Intern, you will contribute to the development and verification of selected IP layout cells used in memory products. Working alongside experienced layout engineers, you will gain hands–on experience with industry–standard layout methodologies and participate in key activities such as floorplanning, placement, routing, and physical verification. You will also have the opportunity to develop automation solutions that improve engineering productivity, design quality, and efficiency through scripting and AI–supported development.

Responsibilities:

• Develop the layout of selected analog and digital IP layout cells under the guidance of experienced layout engineers.
• Perform Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification and document findings.
• Create and deliver technical reports summarizing design work, verification results, and key lessons learned.
• Design and implement a SKILL-based automation solution to improve layout design or verification processes, increasing engineering efficiency and quality.
• Support engineering activities through AI-assisted development methodologies and productivity tools.

Minimum Qualifications:

• Student pursuing a Bachelor's degree in Electrical Engineering, Electronics Engineering, Mechatronics, Robotics, Nanotechnology, Computer Engineering, or a related field, preferably within the final two semesters of study.
• Expected graduation date of December 2027.
• Experience with at least one scripting language such as Python, Perl, or similar.
• Strong time management and organizational skills with the ability to work efficiently on multiple tasks.
• Effective verbal and written communication skills.

Preferred Qualifications:

• Academic or internship experience related to semiconductor layout design processes.
• Understanding of Design Rule Checks (DRC) and Layout Versus Schematic (LVS) analysis.
• Applying AI applications in semiconductor development.
• Experience using Electronic Design Automation (EDA) tools such as Cadence or Synopsys.
• Interest in semiconductor memory technologies and physical design methodologies.

Intern Junior- Non Mfg.

Relocation Level: TBD

Before Getting Started

Please review Micron’s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that:

• Hiring managers may view your performance appraisals, original resume, transcripts or other performance–related documentation in your personal file. This information will be held in confidence.
• If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.

The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time–off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.