DRAM IP Layout Intern — Automation & AI

Micron Technology; Tlaquepaque; On-site; MXN 45,000 - 89,000; Full time

Job summary

Micron Technology is seeking a Layout Design Engineering Intern to contribute to the development and verification of IP layout cells used in memory products. You will work with experienced layout engineers on floorplanning, placement, routing and physical verification.

You will also gain hands-on experience with scripting and AI-supported development to improve engineering productivity and design quality. This internship offers exposure to CAD tools and industry standards.

Qualifications

• Pursuing a Bachelor's degree in a relevant engineering field.
• Expected graduation December 2027.

Responsibilities

• Develop the layout of selected analog and digital IP layout cells under guidance of experienced layout engineers.
• Perform DRC and LVS verification and document findings.
• Create and deliver technical reports summarizing design work and verification results.
• Design and implement a SKILL-based automation solution to improve layout design or verification processes.
• Support engineering activities through AI-assisted development methodologies and productivity tools.

Skills

Scripting

Time management

Communication

Problem solving

Education

Electrical Engineering

Electronics Engineering

Mechatronics

Robotics

Nanotechnology

Computer Engineering

Tools

Cadence

Synopsys

Job description

Micron Technology is seeking a Layout Design Engineering Intern to contribute to the development and verification of IP layout cells used in memory products. You will work with experienced layout engineers on floorplanning, placement, routing and physical verification.

You will also gain hands-on experience with scripting and AI-supported development to improve engineering productivity and design quality. This internship offers exposure to CAD tools and industry standards.