DRAM Design Layout Engineer – Design Tech Lead

Micron

Jalisco

Presencial

MXN 450.000 - 750.000

Jornada completa

Hace 2 días
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Descripción de la vacante

Micron Technology, Inc. seeks a DRAM Design Engineer to translate schematics into DRAM IP layouts and drive physical verification for multiple projects. You will coordinate with global teams and guide junior designers to meet tight deadlines.

You will apply Cadence Virtuoso and Mentor Calibre tools, optimize layouts for performance, area and yield, and contribute to continuous improvement in layout methodologies. Based in Mexico, this role emphasizes collaboration and technical leadership.

Formación

  • Proven experience in CMOS layout for advanced processes.
  • Ability to perform IP layout development and physical verification.
  • Strong understanding of layout fundamentals and design rules.

Responsabilidades

  • Design and develop IP layouts used in DRAM chips.
  • Perform LVS/DRC/EM checks and document results.
  • Deliver block-level layouts on schedule with quality.
  • Lead and mentor sub-block layout workstreams.
  • Coordinate with global teams to ensure project success.
  • Plan layouts and present material for reviews.

Conocimientos

Layout design
CMOS process
IP layout development
Physical verification
Cadence Virtuoso
Mentor Calibre
Leadership
Team collaboration

Educación

BE/BTech in Electronic/VLSI
MTech in related field
Diploma in electronics/VLSI

Herramientas

Cadence Virtuoso
Mentor Calibre
Parasitic analysis tools
Layout automation (Skill coding)

Descripción del empleo

Micron Technology, Inc. seeks a DRAM Design Engineer to translate schematics into DRAM IP layouts and drive physical verification for multiple projects. You will coordinate with global teams and guide junior designers to meet tight deadlines.

You will apply Cadence Virtuoso and Mentor Calibre tools, optimize layouts for performance, area and yield, and contribute to continuous improvement in layout methodologies. Based in Mexico, this role emphasizes collaboration and technical leadership.

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