DRAM Design Technology Layout Engineer

Micron Technology, Inc; Tlaquepaque; Presencial; MXN 693.962 - 1.040.943; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental, and vision plans

Paid family leave

Robust paid time-off program

Paid holidays

Descripción de la vacante

Micron Technology, Inc is looking for a DRAM Design Technology Layout Engineer in Tlaquepaque, Jalisco. You will design and develop IP layouts for DRAM chips, ensuring engineering and process-related criteria are adhered to, while collaborating globally to ensure project success.

Ideal candidates will have a Bachelor's degree in Electrical Engineering or similar, with at least 3 years of layout design experience, and expertise in Cadence tools. The position offers comprehensive benefits including medical and paid time off.

Formación

• Minimum of 3 years of experience in layout design.
• Ability to perform IP layout development and physical verification.
• Expertise in layout area and routing optimization.

Responsabilidades

• Design and develop IP layouts used in DRAM chips.
• Perform layout verification and provide quality checks.
• Deliver block-level layouts on time.

Conocimientos

Layout design in advanced CMOS process

IP layout development

Electro-migration

Cadence tools

Problem-solving skills

Educación

Bachelor’s degree in Electrical, Electronics, Mechatronics, Robotics, Biomedical Engineering or related field

Herramientas

Cadence Virtuoso

Mentor Calibre

Descripción del empleo

Job ID and Title

JR101718 – DRAM Design Technology Layout Engineer

Overview

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a member of the DRAM Design Engineering Group, you will translate schematics into layout for the creation of fabrication reticules and ensure all engineering and process-related criteria are met for assigned DRAM products. You will organize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution. Your work will involve applying multiple layout techniques for the design and verification of digital and analog circuits, understanding various circuit design protocols, fabric processes, mask generation techniques and tape‑out procedures.

Responsibilities

• Design and develop IP layouts used in DRAM chips.
• Perform layout verification (LVS/DRC/EM) and provide quality checks and documentation.
• Deliver block‑level layouts on time with acceptable quality.
• Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules in multiple project environments.
• Contribute to effective project management.
• Plan and detail layout plans, presenting material for global teams to review.
• Collaborate with engineering teams in India, Japan, the U.S., and other global locations to ensure layout project success.

Minimum Qualifications

• Bachelor’s degree or equivalent experience in Electrical, Electronics, Mechatronics, Robotics, Biomedical Engineering, or a related field.
• Minimum of 3years of experience in layout design in advanced CMOS process.
• Ability to perform IP layout development and physical verification activities for complex designs per specifications.
• Expertise in layout area and routing optimization, design rules, yield and reliability issues.
• Knowledge of layout fundamentals such as electro-migration, latch‑up, coupling, crosstalk, IR‑drop, parasitic analysis, and matching.
• Adequate knowledge of schematics and collaboration with circuit designers and CAD team.
• Understanding of layout effects on circuit performance (speed, capacitance, power, area).
• Excellent problem‑solving skills in area, power, performance, and physical verification of custom layout.
• Experience with Cadence tools, including Virtuoso schematic editor, Virtuoso layout L, XL & verification tools like Mentor Calibre, and proficiency in device matching, parasitic analysis, electron migration, and isolation techniques.
• Ability to work in a team environment and provide technical support to colleagues.

Preferred Qualifications

• Knowledge of Skill coding and layout automation.
• Self‑motivated, hardworking, goal‑oriented with excellent verbal and written communication skills.
• Leadership skills and ability to multitask.

Job Details

Level: E2 – Layout/Mask Designer

Relocation Level: TBD

Benefits

Micron offers medical, dental and vision plans, income protection programs, paid family leave, a robust paid time‑off program, and paid holidays. For additional information, please see the Benefits Guide posted on Benefits | Micron Technology, Inc.

Equal Opportunity

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.