Senior Physical Design Engineer: RTL-to-GDSII Lead

OPENCHIP & SOFTWARE TECHNOLOGIES; Roma; Hybrid; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Hybrid work environment

Rome-based role

Collaborative research partnerships

Job summary

OPENCHIP & SOFTWARE TECHNOLOGIES is seeking a Physical Design Senior Engineer to own the implementation of highly complex digital blocks, including high-speed interfaces and automotive low-power modules. You will ensure the design intent is preserved while optimizing during physical implementation.

You will lead RTL-to-GDSII flow with floorplanning, P&R, CTS, manage timing and constraints, and drive early timing closure using ECOs.

Qualifications

• 10+ years of professional experience in Semiconductor Physical Design and Digital Implementation.
• Expert knowledge of SDC format and ability to write, debug and manage complex constraints.
• Hands-on experience with STA tools (PrimeTime or Tempus) in advanced tech nodes and automotive contexts.
• Proficiency in Clock Domain Crossing (CDC) analysis and verification.
• Excellent scripting capabilities (Tcl, Python, or Perl) for automation and reporting.

Responsibilities

• Advanced Physical Implementation & Constraint Ownership.
• RTL-to-GDSII execution including Floorplanning, Place and Route, and CTS.
• Drive a constraint-driven approach to minimize iterations and optimize results.
• Identify and resolve routing congestion and timing bottlenecks proactively.
• Manage SDC constraints, clean/regenerate timing constraints for silicon reality.
• Deliver complex timing closure and perform ECOs at the gate level.
• Validate Signal Integrity and Power Integrity to ensure robust sign-off.

Skills

Semiconductor Physical Design

Scripting (Tcl/Python/Perl)

Tools

PrimeTime

Tempus

Job description

OPENCHIP & SOFTWARE TECHNOLOGIES is seeking a Physical Design Senior Engineer to own the implementation of highly complex digital blocks, including high-speed interfaces and automotive low-power modules. You will ensure the design intent is preserved while optimizing during physical implementation.

You will lead RTL-to-GDSII flow with floorplanning, P&R, CTS, manage timing and constraints, and drive early timing closure using ECOs.