Lead Digital Design Architect - High-Speed IPs & Signoff

Infineon Technologies; Cascina Priora; In loco; EUR 57.600 - 79.200; Tempo pieno

Descrizione del lavoro

Infineon Technologies in Italy is seeking a Principal Digital Design Engineer to lead the RTL/Verilog design of advanced Analogue/Mixed‑Signal IPs and drive silicon bring‑up.

You will own the full digital design flow RTL‑to‑GDS, coordinate with System and Analogue teams, and mentor engineering staff to achieve robust timing closure and design excellence.

The role requires 10+ years of RTL experience and fluent English, with a strong leadership mindset and hands‑on expertise in high‑speed SerDes.

Competenze

• 10+ years of RTL design experience for Analogue/Mixed‑Signal IPs.
• Leadership experience guiding engineering teams.
• Expert in Verilog/SystemVerilog.

Mansioni

• Lead the Digital Design team from specification to silicon bring‑up.
• Design digital components for analog/mixed‑signal IPs including high‑speed SerDes, PHYs, PLLs.
• Own digital signoff across RTL‑to‑GDS, LEC, linting, CDC/RDC, ATPG.

Conoscenze

Leadership

Verilog/SystemVerilog

RTL design

Digital design flow

English fluent

Formazione

Bachelor's degree in Electrical Engineering or related field

Advanced degree (MS/PhD) preferred

Descrizione del lavoro

Infineon Technologies in Italy is seeking a Principal Digital Design Engineer to lead the RTL/Verilog design of advanced Analogue/Mixed‑Signal IPs and drive silicon bring‑up.

You will own the full digital design flow RTL‑to‑GDS, coordinate with System and Analogue teams, and mentor engineering staff to achieve robust timing closure and design excellence.

The role requires 10+ years of RTL experience and fluent English, with a strong leadership mindset and hands‑on expertise in high‑speed SerDes.