RTL-to-GDS SoC Physical Implementation Engineer

Infineon Technologies AG; Padova; On-site; EUR 38,000 - 53,000; Full time

Job summary

Infineon Technologies AG in Padova, Italy seeks a SoC Physical Implementation Engineer in our R&D team. You will perform floor planning, partitioning, placement and routing at chip and block level, while optimizing timing, power and area to meet design specs.

You will drive timing closure, verification and sign-off in a mixed Digital/Analog flow, and develop P&R scripts to automate the flow. The role requires 3+ years in SoC implementation, strong scripting skills (TCL, Python/Perl) and

Qualifications

• Electrical/Electronic Engineering degree or equivalent with microelectronic device knowledge.
• At least 3 years of SoC implementation experience from RTL to GDS in UNIX.
• Experience with RTL to GDS flow: synthesis, P&R, STA, sign-off in sub-micron tech.
• Experience with P&R work-packages planning, effort estimation and risk management.
• Strong TCL, Python and/or Perl scripting skills; DFT experience a plus.
• Fluent in English.

Responsibilities

• Perform floor planning, partitioning, placement and routing at chip and block level.
• Optimize timing, power and area to design specs.
• Achieve timing closure and perform verification and sign-off.
• Develop P&R scripts for development flow automation.
• Collaborate with digital design and analog layout teams.
• Participate in design reviews, FMEA, and generate design reports.
• Estimate effort and plan related work packages; interface with project team.

Skills

Floor planning

Partitioning

Placement & Routing

Timing

Power

Area

Timing closure

Verification

Sign-off

TCL scripting

Python scripting

Perl scripting

DFT

Innovus

Genus

RTL to GDS flow

Synthesis

UNIX environment

Education

Electrical/Electronic Engineering degree

Tools

Innovus

Genus

Synopsys

Cadence

Job description

Infineon Technologies AG in Padova, Italy seeks a SoC Physical Implementation Engineer in our R&D team. You will perform floor planning, partitioning, placement and routing at chip and block level, while optimizing timing, power and area to meet design specs.

You will drive timing closure, verification and sign-off in a mixed Digital/Analog flow, and develop P&R scripts to automate the flow. The role requires 3+ years in SoC implementation, strong scripting skills (TCL, Python/Perl) and