Physical Design Senior Engineer

OPENCHIP & SOFTWARE TECHNOLOGIES; Roma; Hybrid; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Hybrid work environment

Rome-based role

Collaborative research partnerships

Job summary

OPENCHIP & SOFTWARE TECHNOLOGIES is seeking a Physical Design Senior Engineer to own the implementation of highly complex digital blocks, including high-speed interfaces and automotive low-power modules. You will ensure the design intent is preserved while optimizing during physical implementation.

You will lead RTL-to-GDSII flow with floorplanning, P&R, CTS, manage timing and constraints, and drive early timing closure using ECOs.

Qualifications

• 10+ years of professional experience in Semiconductor Physical Design and Digital Implementation.
• Expert knowledge of SDC format and ability to write, debug and manage complex constraints.
• Hands-on experience with STA tools (PrimeTime or Tempus) in advanced tech nodes and automotive contexts.
• Proficiency in Clock Domain Crossing (CDC) analysis and verification.
• Excellent scripting capabilities (Tcl, Python, or Perl) for automation and reporting.

Responsibilities

• Advanced Physical Implementation & Constraint Ownership.
• RTL-to-GDSII execution including Floorplanning, Place and Route, and CTS.
• Drive a constraint-driven approach to minimize iterations and optimize results.
• Identify and resolve routing congestion and timing bottlenecks proactively.
• Manage SDC constraints, clean/regenerate timing constraints for silicon reality.
• Deliver complex timing closure and perform ECOs at the gate level.
• Validate Signal Integrity and Power Integrity to ensure robust sign-off.

Skills

Semiconductor Physical Design

Scripting (Tcl/Python/Perl)

Tools

PrimeTime

Tempus

Job description

The Role

As a Physical Design Senior Engineer, you will take technical ownership of the implementation for highly complex digital blocks, including high-speed interfaces, mixed-signal control logic, and automotive low‑power modules. Working at the intersection of logic and physics, you are responsible for ensuring that the functional design intent is fully preserved while being highly optimized during the physical implementation phase.

Key Responsibilities

• Advanced Physical Implementation & Constraint Ownership
• Full-Flow Execution: Take technical ownership of the RTL-to-GDSII implementation, including Floorplanning, Place and Route (P&R), and Clock Tree Synthesis (CTS).
• Execution Strategy: Drive a "constraint-driven" approach to minimize iterations and ensure optimal physical results.
• Bottleneck Resolution: Analyze functional contexts to identify and resolve routing congestion and timing bottlenecks proactively.
• Constraint Maintenance: Hands‑on management of SDC constraints at every stage; responsible for cleaning, regenerating, and validating timing constraints to ensure they reflect silicon reality (e.g., Multi-Cycle Paths, False Paths).
• Timing Closure & ECO Implementation
• Sign-off Focus: Deliver complex timing closure for designs with multiple clock domains and asynchronous interfaces using DMSA and OCV/AOCV/POCV techniques.
• Advanced ECO Execution: Implement Engineering Change Orders (ECO) at the gate level and propose physical-level adjustments when required to meet timing or power targets.
• Design Integrity: Perform and validate Signal Integrity (SI) and Power Integrity (IR-Drop/EM) analyses to ensure robust sign-off.

Requirements (Must Have)

• Experience: 10+ years of professional experience in Semiconductor Physical Design and Digital Implementation.
• SDC Expertise: Expert knowledge of SDC format with the ability to write, debug, and manage complex constraints for Multi-Mode Multi-Corner (MMMC) designs.
• Timing & STA: Solid hands‑on experience with STA tools (PrimeTime or Tempus) and managing violations in advanced technology nodes or critical environments (e.g., Automotive).
• CDC Knowledge: Proficiency in Clock Domain Crossing (CDC) analysis and verification.
• Automation Skills: Excellent scripting capabilities (Tcl, Python, or Perl) for flow automation and report analysis.

Preferred Qualifications (Nice To Have)

• RTL-to-GDSII Integration: Proven experience interfacing with Front-End teams to optimize RTL for better physical synthesis and routability.
• Manufacturing & Reliability: Practical experience implementing DFM (Design for Manufacturing) rules and performing Yield analysis to ensure high-volume production stability.
• Advanced Power Methodologies: Hands‑on experience with Low Power design flows using UPF or CPF, including the implementation of power-gating and multi-voltage domains.
• Domain-Specific Compliance: Familiarity with Automotive safety standards (ISO 26262), specifically regarding physical redundancy or electromigration (EM) requirements for mission-critical chips.
• Hierarchy & Partitioning: Experience managing large-scale hierarchical designs, including partitioning and top-level integration challenges.

What Do We Offer?

• Join a highly innovative microelectronics company working at the forefront of RISC-V and advanced SoC technologies.
• Opportunity to play a key technical leadership role bridging industry and public research.
• Collaboration with top-tier research institutions and industrial partners across Europe.
• Flexible working conditions and hybrid work environment.
• Competitive remuneration aligned with seniority and expertise.
• Position based in Rome.

We are looking for outstanding people willing to join our mission to change this industry and help to build a better world

At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.