Senior High-Speed Digital Design Lead (RTL/Architecture)

ams OSRAM; Lombardia; In loco; EUR 120.000 - 180.000; Tempo pieno

Vantaggi offerti da questo lavoro

Equal opportunity employer

Descrizione del lavoro

ams OSRAM is seeking a technical leader for architecture and RTL development of high-speed digital subsystems in communication ICs and mixed-signal SoCs. Define digital architectures and steer RTL design from integration to delivery.

The role requires MSc/PhD in EE, 10+ years in digital IC design, and expertise in Verilog/SystemVerilog, with familiarity with UCIe/PCIe protocols and CMOS FinFET/FD-SOI processes. Mentoring and cross-team collaboration are essential aspects of the job.

Competenze

• MSc or PhD in Electrical Engineering
• 10+ years digital IC design experience
• RTL design (Verilog/SystemVerilog)
• High-speed digital IC design experience for communication or mixed-signal SoC products; knowledge of high-speed interfaces such as UCIe, PCIe or similar protocols is an advantage
• Interface protocols and clock-domain crossing
• Synthesis and timing analysis
• Advanced CMOS node experience, including FinFET and/or FD-SOI

Mansioni

• Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products
• Define digital subsystem architectures
• Lead RTL development and integration
• Drive design reviews and quality standards
• Support verification and implementation teams
• Mentor design engineers

Conoscenze

RTL design

High-speed IC design

Interface protocols

Synthesis and timing analysis

Clock-domain crossing

Verilog/SystemVerilog

Formazione

MSc or PhD in Electrical Engineering

Descrizione del lavoro

ams OSRAM is seeking a technical leader for architecture and RTL development of high-speed digital subsystems in communication ICs and mixed-signal SoCs. Define digital architectures and steer RTL design from integration to delivery.

The role requires MSc/PhD in EE, 10+ years in digital IC design, and expertise in Verilog/SystemVerilog, with familiarity with UCIe/PCIe protocols and CMOS FinFET/FD-SOI processes. Mentoring and cross-team collaboration are essential aspects of the job.