Senior Design Engineer - Digital Implementation (AI-Driven)

Micron Technology, Inc.; Avezzano; Remote; EUR 43,000 - 74,000; Full time

Benefits offered by this job

Meal vouchers

Corporate welfare

Remote working days allowance

Supplementary health insurance

Life coverage

Employee assistance program

Job summary

Micron Technology, Inc. Avezzano, Italy seeks a Design Engineer to drive RTL-to-GDSII physical implementation for advanced NAND flash digital blocks. You will lead floorplanning, placement, clock tree synthesis, and routing with collaboration across RTL, DFT, analog, and verification teams.

Expect to optimize performance, power, and area while ensuring tape-out readiness. You will leverage scripting to automate flows, enhance yield, and apply AI-assisted techniques to timing, congestion, and

Qualifications

• Hands-on experience with digital physical design and automated place-and-route flows for complex ASICs/SOC/memory.
• Strong knowledge of floorplanning, clock distribution, timing closure, and physical verification.
• Experience with scripting and flow automation in Tcl, Python, or Perl.

Responsibilities

• Own RTL-to-GDSII physical implementation for complex digital blocks and subsystems.
• Develop floorplans, power distribution, placement, clock tree synthesis, and routing.
• Drive timing closure across multi-mode/multi-corner scenarios.
• Perform physical sign-off checks: DRC, LVS, antenna, SI, congestion, IR-drop, EM, power.
• Collaborate with RTL, DFT, analog, layout, CAD, and verification teams.
• Develop scripts and reusable methodologies to automate flows and improve throughput.

Skills

Digital physical design

RTL-to-GDSII

Scripting (Tcl, Python, Perl)

Problem solving

Documentation & communication

Education

M.S. or Ph.D. in Electrical Engineering or related field

Tools

Cadence Innovus/Tempus

Synopsys Fusion Compiler/IC Compiler II/PrimeTime

Python

Tcl

Perl

Job description

Micron Technology, Inc. Avezzano, Italy seeks a Design Engineer to drive RTL-to-GDSII physical implementation for advanced NAND flash digital blocks. You will lead floorplanning, placement, clock tree synthesis, and routing with collaboration across RTL, DFT, analog, and verification teams.

Expect to optimize performance, power, and area while ensuring tape-out readiness. You will leverage scripting to automate flows, enhance yield, and apply AI-assisted techniques to timing, congestion, and