PMU Verification Engineer: RTL/UVM & Silicon Validation

Apple; Livorno; In loco; EUR 50.000 - 70.000; Tempo pieno

Descrizione del lavoro

A leading technology company located in Italy is seeking a dedicated Design Verification Engineer. In this critical role, you will ensure bug-free first silicon for mixed-signal designs through collaboration with design engineers. Responsibilities include developing verification plans, managing test environments, and utilizing SystemVerilog and UVM for verification. Ideal candidates will hold a master's degree and possess strong communication skills. Join us to innovate and create products that enhance daily lives.

Competenze

• Master's degree in Electrical Engineering, Embedded Systems, Computer Science or related field.
• Excellent communication and interpersonal skills.
• Deep knowledge of SystemVerilog and UVM.

Mansioni

• Develop verification plans in coordination with design leads and architects.
• Be responsible for planning, building and maintaining verification test bench components.
• Generate directed and constrained random tests, run simulations, and debug design issues.

Conoscenze

Communication skills

Collaboration

SystemVerilog

UVM

Test-bench development

Coverage analysis

Formazione

Master’s degree in Electrical Engineering or related field

Strumenti

Python

Perl

TCL

Descrizione del lavoro

A leading technology company located in Italy is seeking a dedicated Design Verification Engineer. In this critical role, you will ensure bug-free first silicon for mixed-signal designs through collaboration with design engineers. Responsibilities include developing verification plans, managing test environments, and utilizing SystemVerilog and UVM for verification. Ideal candidates will hold a master's degree and possess strong communication skills. Join us to innovate and create products that enhance daily lives.