Lead Physical ASIC Design Implementation Engineer

imec; Napoli; On-site; EUR 70,000 - 110,000; Full time

Job summary

Imec's Physical Digital Implementation Group in Napoli seeks two Experienced ASIC Design Implementation Engineers to drive full flow from netlist-in to GDSII-out. You will handle back-end design across technology nodes, lead in senior projects, and interact directly with customers to meet specifications.

You will set up implementation flows, perform floorplanning, timing closure, and sign-off steps using Cadence Innovus, Tempus, Quantus, and Voltus.

Qualifications

• Master’s degree in Electronics Engineering.
• 8+ years of experience in physical implementation, including technology nodes from 12 nm down to 2 nm.
• Experience with hierarchical, multi-block, and top-level chip designs.
• Strong Cadence digital implementation experience, particularly Innovus.
• Experience with Tempus, Quantus, and Voltus preferred.
• Knowledge of low-power design techniques (clock gating, multiple voltage domains, power gating, state retention).
• Strong knowledge of STA, timing closure, SI, PI, and physical verification.
• Excellent communication skills and ability to work in international/multicultural environments.
• Fluency in English.
• Senior role: experience as Technical Lead coordinating team members.

Responsibilities

• Set up and configure the implementation flow for the selected technology node, foundry requirements, and library set.
• Implement low-power designs using UPF.
• Floorplanning, macro placement, and power-grid design.
• Timing-driven placement and placement optimization.
• Static timing analysis and design optimization for setup timing.
• Implement Clock Tree Synthesis.
• Perform scan-chain reordering and re-stitching.
• Execute timing-driven routing with signal-integrity analysis.
• In-place optimization to achieve timing closure across modes and corners.
• Debug setup and hold violations.
• Sign-off parasitic extraction using Quantus and SPEF generation.
• Sign-off static timing analysis using Tempus.
• Sign-off power and EM/IR analysis using Voltus.
• Physical verification (DRC/ERC/LVS/antenna checks) and logic equivalence checking.
• Support final sign-off closure and tape-out.
• Collaborate with customers to discuss specifications and project status.

Skills

Strong communication

Customer interaction

English fluency

Problem solving

Leadership (senior)

Education

Master’s degree in Electronics Engineering

Tools

Cadence Innovus

Tempus

Quantus

Voltus

Job description

Imec's Physical Digital Implementation Group in Napoli seeks two Experienced ASIC Design Implementation Engineers to drive full flow from netlist-in to GDSII-out. You will handle back-end design across technology nodes, lead in senior projects, and interact directly with customers to meet specifications.

You will set up implementation flows, perform floorplanning, timing closure, and sign-off steps using Cadence Innovus, Tempus, Quantus, and Voltus.