Senior Analog IC Layout Engineer — Tape-Out Leader

NXP Semiconductors NV; Sicilia; On-site; EUR 51,000 - 70,000; Full time

Job summary

NXP Semiconductors NV in Italy seeks a Senior Layout Engineer to drive the physical implementation of complex analog/mixed-signal IC designs from floorplanning to tape-out. You will collaborate with design, verification, and technology teams, delivering milestones and mentoring junior engineers.

The role requires deep expertise in layout methodologies, problem-solving, and strong English communication. Expect to work on advanced nodes with tight schedules and a competitive benefits package.

Qualifications

• 8–12+ years of custom analog/mixed-signal layout experience in deep sub-micron CMOS.
• Expert in Cadence Virtuoso XL, Floorplanning, Constraint Driven Layout, and PVS DRC/LVS/ERC.
• Strong knowledge of matching, common centroid, shielding, EM/IR, high-speed routing, parasitics, and DFM practices.
• Proven experience leading analog-on-top and digital-on-top chip layouts.
• Fluent in English.

Responsibilities

• Lead the layout implementation of complex analog, mixed-signal blocks.
• Drive floorplanning, routing strategies, and layout optimization to meet performance, area, power, reliability, and manufacturability requirements.
• Perform physical verification activities, including DRC, LVS, ERC, EM/IR, latch-up, density, and reliability checks.
• Collaborate with design, verification, technology, and product engineering teams to resolve layout-related challenges and achieve milestones.
• Support advanced-node technologies, including FinFET processes, and contribute to methodology improvements and best practices.
• Provide technical guidance and mentorship to junior engineers and contractors.
• Assess project risks, estimate layout effort, and drive execution to meet aggressive schedules.

Skills

Analog layout

Device matching

Layout optimization

High-speed routing

Education

BSEE or MSEE

Tools

Cadence Virtuoso XL

PVS DRC/LVS/ERC

Perl scripting

Job description

NXP Semiconductors NV in Italy seeks a Senior Layout Engineer to drive the physical implementation of complex analog/mixed-signal IC designs from floorplanning to tape-out. You will collaborate with design, verification, and technology teams, delivering milestones and mentoring junior engineers.

The role requires deep expertise in layout methodologies, problem-solving, and strong English communication. Expect to work on advanced nodes with tight schedules and a competitive benefits package.