Lead Analog IC Layout Engineer for MCU Tapeouts

NXP Semiconductors NV; Catania; On-site; EUR 51,000 - 70,000; Full time

Benefits offered by this job

Annual incentive opportunities

Equity

Competitive benefits package

Job summary

NXP Semiconductors NV in Italy is seeking an experienced Senior Layout Engineer to lead physical implementation of complex analog, mixed-signal, and custom IC designs. You will drive layout execution from floorplanning through tape-out, delivering performance, quality, and schedule targets.

You will mentor junior engineers, contribute to layout methodology improvements, and collaborate across design, verification, and technology teams to mitigate risk and ensure successful silicon delivery.

Qualifications

• BSEE or MSEE required with advanced degree preferred.
• 8–12+ years’ deep sub-micron analog/mixed-signal layout experience.
• Expert in Cadence Virtuoso XL, floorplanning, constraint-driven layout and PVS DRC/LVS/ERC.
• Strong knowledge of matching, centroid, shielding, EM/IR, high-speed routing, parasitics and DFM practices.
• Proven experience leading analog-on-top and digital-on-top layouts.
• Experience with floorplanning, power distribution, ESD and multiple voltage domains.
• Familiarity with PLL, OSC, ADC, DAC, LDO, Bandgap and high-speed interfaces.
• Excellent communication and cross-functional leadership skills; fluent in English.

Responsibilities

• Lead the layout implementation of analog, mixed-signal, and custom digital blocks.
• Drive floorplanning, device matching, routing strategies, and layout optimization for performance and manufacturability.
• Perform and review DRC, LVS, ERC, EM/IR, latch-up, density and reliability checks.
• Collaborate with design, verification, technology, and product engineering to resolve layout challenges and hit milestones.
• Support advanced-node technologies, including FinFET processes; contribute to methodology improvements and best practices.
• Provide technical guidance and mentorship to junior engineers and contractors.
• Assess project risks, estimate layout effort, and drive execution to meet aggressive schedules.

Skills

Analog layout

Mixed-signal layout

Floorplanning

EDA tooling

Mentoring

English fluency

Education

BSEE or MSEE

Tools

Cadence Virtuoso XL

PVS DRC/LVS/ERC

Constraint-Driven Layout

Perl scripting

Job description

NXP Semiconductors NV in Italy is seeking an experienced Senior Layout Engineer to lead physical implementation of complex analog, mixed-signal, and custom IC designs. You will drive layout execution from floorplanning through tape-out, delivering performance, quality, and schedule targets.

You will mentor junior engineers, contribute to layout methodology improvements, and collaborate across design, verification, and technology teams to mitigate risk and ensure successful silicon delivery.