Physical ASIC Design Implementation Engineer - Naples

imec; Napoli; Vor Ort; EUR 70.000 - 110.000; Vollzeit

Zusammenfassung

Imec's Physical Digital Implementation Group in Napoli seeks two Experienced ASIC Design Implementation Engineers to drive full flow from netlist-in to GDSII-out. You will handle back-end design across technology nodes, lead in senior projects, and interact directly with customers to meet specifications.

You will set up implementation flows, perform floorplanning, timing closure, and sign-off steps using Cadence Innovus, Tempus, Quantus, and Voltus.

Qualifikationen

• Master’s degree in Electronics Engineering.
• 8+ years of experience in physical implementation, including technology nodes from 12 nm down to 2 nm.
• Experience with hierarchical, multi-block, and top-level chip designs.
• Strong Cadence digital implementation experience, particularly Innovus.
• Experience with Tempus, Quantus, and Voltus preferred.
• Knowledge of low-power design techniques (clock gating, multiple voltage domains, power gating, state retention).
• Strong knowledge of STA, timing closure, SI, PI, and physical verification.
• Excellent communication skills and ability to work in international/multicultural environments.
• Fluency in English.
• Senior role: experience as Technical Lead coordinating team members.

Aufgaben

• Set up and configure the implementation flow for the selected technology node, foundry requirements, and library set.
• Implement low-power designs using UPF.
• Floorplanning, macro placement, and power-grid design.
• Timing-driven placement and placement optimization.
• Static timing analysis and design optimization for setup timing.
• Implement Clock Tree Synthesis.
• Perform scan-chain reordering and re-stitching.
• Execute timing-driven routing with signal-integrity analysis.
• In-place optimization to achieve timing closure across modes and corners.
• Debug setup and hold violations.
• Sign-off parasitic extraction using Quantus and SPEF generation.
• Sign-off static timing analysis using Tempus.
• Sign-off power and EM/IR analysis using Voltus.
• Physical verification (DRC/ERC/LVS/antenna checks) and logic equivalence checking.
• Support final sign-off closure and tape-out.
• Collaborate with customers to discuss specifications and project status.

Kenntnisse

Strong communication

Customer interaction

English fluency

Problem solving

Leadership (senior)

Ausbildung

Master’s degree in Electronics Engineering

Tools

Cadence Innovus

Tempus

Quantus

Voltus

Jobbeschreibung

We are looking for two Physical ASIC Design Implementation Engineers to strengthen our Physical Digital Implementation Group, in Naples. One of the positions is aimed at a more senior profile, who will take on a technical lead role in larger projects. You will work on full back-end projects, covering the complete flow from netlist-in to GDSII-out. The role includes both top-level chip implementation and block-level designs across technology nodes. A thorough understanding of the complete Cadence Innovus Place-and-Route flow is required.

What you will do

For more than 25 years, imec has provided ASIC prototyping and production services to companies and universities worldwide. Imec supports its customers in designing integrated circuits and bringing them from the initial prototype stage through to production. Our customer base includes more than 900 universities and companies worldwide.

To further strengthen the Physical Digital Implementation Group, also known as the Back-End Group, within DSRD, we are looking for a highly motivated and experienced engineer.

As part of imec, DSRD has extensive industrial experience, strong relationships with leading semiconductor foundries, and long-standing collaborations with major EDA tool vendors and IP providers. The unit supports customers worldwide in the design, physical implementation, prototyping, fabrication, and testing of advanced electronic products.

As a Physical ASIC Design Implementation Engineer, you will work directly with customers on future projects and contribute to the complete Cadence Innovus Place-and-Route and sign-off flow.

Your responsibilities will include:

• Setting up and configuring the implementation flow for the selected technology node, foundry requirements, and library set
• Setting up and implementing low-power designs using UPF
• Performing floorplanning, macro placement, and power-grid design
• Executing timing-driven placement and placement optimization
• Performing static timing analysis and design optimization for setup timing
• Implementing Clock Tree Synthesis
• Performing scan-chain reordering and re-stitching
• Executing timing-driven routing, including signal-integrity analysis
• Performing in-place optimization to achieve timing closure across all required modes and corners
• Debugging and resolving setup and hold violations
• Performing sign-off parasitic extraction using Quantus and generating SPEF files
• Performing sign-off static timing analysis using Tempus
• Performing sign-off power and EM/IR analysis using Voltus
• Executing physical verification, including DRC, ERC, LVS, and antenna checks
• Performing logic equivalence checking
• Supporting final sign-off closure and tape-out

For hierarchical designs, you may take responsibility for design partitioning and derive timing budgets and constraints for individual sub-blocks from the top-level SDC. You will work closely with the Physical Design Implementation Team throughout the entire chip-design cycle to drive timing, power, and physical sign-off closure for tape-out. You will also interact directly with customers to discuss design specifications, implementation requirements, technical issues, and project status.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology in Naples, Italy. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow.

We are committed to being an inclusive employer (http://www.imec-int.com/en/careers#diversity) and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. In everything we do, your future colleagues are guided by the imec values of passion, excellence, connectedness, and integrity. We commit to supporting and guiding you in this process, not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

Who you are

• You hold a Master’s degree in Electronics Engineering.
• You have at least 8 years of experience in physical implementation, including experience with advanced technology nodes from 12 nm down to 2 nm.
• You have experience with hierarchical, multi-block, and top-level chip designs.
• You have strong experience with the Cadence digital implementation flow, particularly Innovus.
• Experience with Tempus, Quantus, and Voltus is highly desirable.
• You have experience with low-power design techniques, including clock gating, multiple voltage domains, power gating, state retention, and switchable power domains.
• You have strong knowledge of static timing analysis, timing closure, signal integrity, power integrity, and physical verification.
• You can debug complex tool, flow, library, constraint, and design-related issues.
• You have excellent communication skills and are comfortable working in an international and multicultural environment.
• Fluency in English is required.
• You enjoy interacting directly with customers and can communicate technical topics clearly and effectively.
• For the senior position specifically: You have experience acting as Technical Lead, coordinating team members, making technical decisions, and managing implementation priorities.